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Title: VHDL Download
 Description: Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
 Downloaders recently: [More information of uploader 戴娜]
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DAI
...\.Xil
...\....\PlanAhead-2948-PC
...\....\.................\ngc2edif
...\....\.................\........\E_lock.edif
...\....\.................\........\_xmsgs
...\....\.................\........\......\ngc2edif.xmsgs
...\....\.................\........\ngc2edif.log
...\DAI.gise
...\DAI.xise
...\E_lock.bld
...\E_lock.cmd_log
...\E_lock.lso
...\E_lock.ncd
...\E_lock.ngc
...\E_lock.ngd
...\E_lock.ngr
...\E_lock.pad
...\E_lock.par
...\E_lock.pcf
...\E_lock.prj
...\E_lock.ptwx
...\E_lock.stx
...\E_lock.syr
...\E_lock.twr
...\E_lock.twx
...\E_lock.ucf
...\E_lock.unroutes
...\E_lock.ut
...\E_lock.xpi
...\E_lock.xst
...\E_lock_envsettings.html
...\E_lock_guide.ncd
...\E_lock_map.map
...\E_lock_map.mrp
...\E_lock_map.ncd
...\E_lock_map.ngm
...\E_lock_map.xrpt
...\E_lock_ngdbuild.xrpt
...\E_lock_pad.csv
...\E_lock_pad.txt
...\E_lock_par.xrpt
...\E_lock_summary.html
...\E_lock_summary.xml
...\E_lock_usage.xml
...\E_lock_xst.xrpt
...\XX.vhd
...\XX_summary.html
...\_ngo
...\....\netlist.lst
...\_xmsgs
...\......\bitgen.xmsgs
...\......\map.xmsgs
...\......\ngdbuild.xmsgs
...\......\par.xmsgs
...\......\pn_parser.xmsgs
...\......\trce.xmsgs
...\......\xst.xmsgs
...\df.ucf
...\e_lock.bgn
...\ipcore_dir
...\iseconfig
...\.........\DAI.projectmgr
...\.........\E_lock.xreport
...\.........\XX.xreport
...\pa.fromHdl.tcl
...\pa.fromNetlist.tcl
...\par_usage_statistics.html
...\pepExtractor.prj
...\planAhead.ngc2edif.log
...\planAhead_pid3036.debug
...\planAhead_run_1
...\...............\planAhead.jou
...\...............\planAhead.log
...\...............\planAhead_run.log
...\planAhead_run_2
...\...............\planAhead.jou
...\...............\planAhead.log
...\...............\planAhead_run.log
...\planAhead_run_3
...\...............\DAI.data
...\...............\........\cache
...\...............\........\.....\E_lock_ngc_zx.edif
...\...............\........\constrs_1
...\...............\........\.........\fileset.xml
...\...............\........\runs
...\...............\........\....\impl_1.psg
...\...............\........\....\runs.xml
...\...............\........\sim_1
...\...............\........\.....\fileset.xml
...\...............\........\sources_1
...\...............\........\.........\fileset.xml
...\...............\........\wt
...\...............\........\..\project.wpc
...\...............\........\..\webtalk_pa.xml
...\...............\DAI.ppr
...\...............\planAhead.jou
...\...............\planAhead.log
...\...............\planAhead_run.log
...\test.vhd
    

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