Description: A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button.
Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively;
The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit;
The upper computer sends and receives the software, and the serial debugger can be used;
When sending and receiving data, instructions are given by two LED respectively.
Play: Auto postback function, receive special characters (custom), change baud rate automatically.
To Search:
File list (Check if you may need any files):
kehshechenxu\clock.qpf
kehshechenxu\clock.qsf
kehshechenxu\clock.qws
kehshechenxu\clock.tis_db_list.ddb
kehshechenxu\clock.vhd
kehshechenxu\clock.vhd.bak
kehshechenxu\db\.cmp.kpt
kehshechenxu\db\clock.ace_cmp.bpm
kehshechenxu\db\clock.ace_cmp.cdb
kehshechenxu\db\clock.ace_cmp.hdb
kehshechenxu\db\clock.acvq.rdb
kehshechenxu\db\clock.asm.qmsg
kehshechenxu\db\clock.asm.rdb
kehshechenxu\db\clock.asm_labs.ddb
kehshechenxu\db\clock.cbx.xml
kehshechenxu\db\clock.cmp.bpm
kehshechenxu\db\clock.cmp.cdb
kehshechenxu\db\clock.cmp.hdb
kehshechenxu\db\clock.cmp.idb
kehshechenxu\db\clock.cmp.logdb
kehshechenxu\db\clock.cmp.rdb
kehshechenxu\db\clock.cmp_merge.kpt
kehshechenxu\db\clock.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
kehshechenxu\db\clock.cycloneive_io_sim_cache.31um_tt_1200mv_0c_slow.hsd
kehshechenxu\db\clock.cycloneive_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
kehshechenxu\db\clock.db_info
kehshechenxu\db\clock.eco.cdb
kehshechenxu\db\clock.fit.qmsg
kehshechenxu\db\clock.hier_info
kehshechenxu\db\clock.hif
kehshechenxu\db\clock.logic_util_heuristic.dat
kehshechenxu\db\clock.lpc.html
kehshechenxu\db\clock.lpc.rdb
kehshechenxu\db\clock.lpc.txt
kehshechenxu\db\clock.map.ammdb
kehshechenxu\db\clock.map.bpm
kehshechenxu\db\clock.map.cdb
kehshechenxu\db\clock.map.hdb
kehshechenxu\db\clock.map.kpt
kehshechenxu\db\clock.map.logdb
kehshechenxu\db\clock.map.qmsg
kehshechenxu\db\clock.map.rdb
kehshechenxu\db\clock.map_bb.cdb
kehshechenxu\db\clock.map_bb.hdb
kehshechenxu\db\clock.map_bb.logdb
kehshechenxu\db\clock.pplq.rdb
kehshechenxu\db\clock.pre_map.hdb
kehshechenxu\db\clock.pti_db_list.ddb
kehshechenxu\db\clock.root_partition.map.reg_db.cdb
kehshechenxu\db\clock.routing.rdb
kehshechenxu\db\clock.rtlv.hdb
kehshechenxu\db\clock.rtlv_sg.cdb
kehshechenxu\db\clock.rtlv_sg_swap.cdb
kehshechenxu\db\clock.sld_design_entry.sci
kehshechenxu\db\clock.sld_design_entry_dsc.sci
kehshechenxu\db\clock.smart_action.txt
kehshechenxu\db\clock.sta.qmsg
kehshechenxu\db\clock.sta.rdb
kehshechenxu\db\clock.sta_cmp.6_slow_1200mv_85c.tdb
kehshechenxu\db\clock.tiscmp.fast_1200mv_0c.ddb
kehshechenxu\db\clock.tiscmp.slow_1200mv_0c.ddb
kehshechenxu\db\clock.tiscmp.slow_1200mv_85c.ddb
kehshechenxu\db\clock.tis_db_list.ddb
kehshechenxu\db\clock.vpr.ammdb
kehshechenxu\db\prev_cmp_clock.qmsg
kehshechenxu\incremental_db\compiled_partitions\clock.db_info
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.cmp.ammdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.cmp.cdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.cmp.dfp
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.cmp.hdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.cmp.logdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.cmp.rcfdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.cdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.dpi
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.cdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.hb_info
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.hdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.sig
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.hdb
kehshechenxu\incremental_db\compiled_partitions\clock.root_partition.map.kpt
kehshechenxu\incremental_db\compiled_partitions\clock.rrp.hdb
kehshechenxu\incremental_db\README
kehshechenxu\output_files\clock.asm.rpt
kehshechenxu\output_files\clock.done
kehshechenxu\output_files\clock.fit.rpt
kehshechenxu\output_files\clock.fit.smsg
kehshechenxu\output_files\clock.fit.summary
kehshechenxu\output_files\clock.flow.rpt
kehshechenxu\output_files\clock.jdi
kehshechenxu\output_files\clock.map.rpt
kehshechenxu\output_files\clock.map.summary
kehshechenxu\output_files\clock.pin
kehshechenxu\output_files\clock.sld
kehshechenxu\output_files\clock.sof
kehshechenxu\output_files\clock.sta.rpt
kehshechenxu\output_files\clock.sta.summary
kehshechenxu\rcvr.vhd
kehshechenxu\rcvr.vhd.bak
kehshechenxu\txmit.vhd
kehshechenxu\txmit.vhd.bak
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