Description: 8-3 priority coding,
1. Learn to design the circuit with Verilog description;
2. Familiar with 8-3 priority encoder and implement its functions in Verilog language;
3. Master the procedure load of Cyclone series FPGA, and master the effect of loading.sof files into the experiment box to achieve the effect of 8-3 priority encoder.
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实验三（1）的指导书.doc
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