AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\an486_ch.pdf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\code\SPI_to_I2C.v
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C.cr.mti
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C.mpf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C.v
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C_test.v
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C_test.v.bak
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\transcript
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\vsim.wlf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master\verilog.psm
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master\_primary.dat
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master\_primary.vhd
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave\verilog.psm
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave\_primary.dat
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave\_primary.vhd
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c\verilog.psm
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c\_primary.dat
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c\_primary.vhd
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test\verilog.psm
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test\_primary.dat
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test\_primary.vhd
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider\verilog.psm
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider\_primary.dat
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider\_primary.vhd
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3\verilog.psm
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3\_primary.dat
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3\_primary.vhd
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\_info
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.asm.qmsg
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.asm_labs.ddb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cbx.xml
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.hdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.logdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.rdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.tdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp0.ddb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.dbp
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.db_info
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.eco.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.fit.qmsg
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.hier_info
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.hif
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.hdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.logdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.qmsg
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.pre_map.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.pre_map.hdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.psp
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.pss
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.rtlv.hdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.rtlv_sg.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.rtlv_sg_swap.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sgdiff.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sgdiff.hdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.signalprobe.cdb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sld_design_entry.sci
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sld_design_entry_dsc.sci
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.syn_hier_info
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.tan.qmsg
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.tis_db_list.ddb
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.asm.rpt
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.done
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.dpf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.fit.rpt
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.fit.smsg
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.fit.summary
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.flow.rpt
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.map.rpt
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.map.smsg
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.map.summary
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.pin
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.pof
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qarlog
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qpf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qsf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qws
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.tan.rpt
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.tan.summary
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.v
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C_assignment_defaults.qdf
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\testbench\SPI_to_I2C_test.v
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\code
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\testbench
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example