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- Other systems
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- 2017-08-02
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- 潘文明
Description: Keystroke dithering
Engineering description
In system design, there are many ways to eliminate the key jitter, both hardware circuit and software design are very mature. In this project, we will use Verilog language to give a specific implementation process, design a program to check the key value, effectively filter the key jitter interval 20 ms burr pulse.
Case Supplement
In this case, we use Verilog HDL language to key debounce is designed, in this process, we can understand the different trigger principle and different constraints, even a simple button function, also has the noticeable jitter filtering process, these are the need to pay attention to the design in later work.
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至简设计法--按键消抖.docx
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