| Filename | Size | Date |
|---|
| readme.txt | 9263 | 2015-01-08
|
| ucf | 0 | 2015-01-08
|
| ucf\top5x2_7to1_ddr_rx.ucf | 5738 | 2015-01-07
|
| ucf\top5x2_7to1_ddr_tx.ucf | 4556 | 2015-01-07
|
| ucf\top5x2_7to1_sdr_rx.ucf | 5355 | 2015-01-07
|
| ucf\top5x2_7to1_sdr_tx.ucf | 4556 | 2015-01-07
|
| Verilog_macros | 0 | 2015-01-08
|
| Verilog_macros\clock_generator_pll_7_to_1_diff_ddr.v | 11892 | 2015-01-07
|
| Verilog_macros\clock_generator_pll_7_to_1_diff_sdr.v | 10699 | 2015-01-07
|
| Verilog_macros\delay_controller_wrap.v | 16573 | 2015-01-07
|
| Verilog_macros\gearbox_4_to_7.v | 7931 | 2015-01-07
|
| Verilog_macros\gearbox_4_to_7_slave.v | 7143 | 2015-01-07
|
| Verilog_macros\n_x_serdes_1_to_7_mmcm_idelay_ddr.v | 8890 | 2015-01-07
|
| Verilog_macros\n_x_serdes_1_to_7_mmcm_idelay_sdr.v | 8325 | 2015-01-07
|
| Verilog_macros\n_x_serdes_7_to_1_diff_ddr.v | 4611 | 2015-01-07
|
| Verilog_macros\n_x_serdes_7_to_1_diff_sdr.v | 4515 | 2015-01-07
|
| Verilog_macros\serdes_1_to_7_mmcm_idelay_ddr.v | 31870 | 2015-01-07
|
| Verilog_macros\serdes_1_to_7_mmcm_idelay_sdr.v | 24887 | 2015-01-07
|
| Verilog_macros\serdes_1_to_7_slave_idelay_ddr.v | 18007 | 2015-01-07
|
| Verilog_macros\serdes_1_to_7_slave_idelay_sdr.v | 15535 | 2015-01-07
|
| Verilog_macros\serdes_7_to_1_diff_ddr.v | 10865 | 2015-01-07
|
| Verilog_macros\serdes_7_to_1_diff_sdr.v | 7482 | 2015-01-07
|
| Verilog_testbench | 0 | 2015-01-08
|
| Verilog_testbench\tb_top5x2_7to1_ddr.v | 4364 | 2015-01-07
|
| Verilog_testbench\tb_top5x2_7to1_sdr.v | 4407 | 2015-01-07
|
| Verilog_top_level_examples | 0 | 2015-01-08
|
| Verilog_top_level_examples\top5x2_7to1_ddr_rx.v | 6596 | 2015-01-07
|
| Verilog_top_level_examples\top5x2_7to1_ddr_tx.v | 6237 | 2015-01-07
|
| Verilog_top_level_examples\top5x2_7to1_sdr_rx.v | 6128 | 2015-01-07
|
| Verilog_top_level_examples\top5x2_7to1_sdr_tx.v | 6136 | 2015-01-07
|
| VHDL_macros | 0 | 2015-01-08
|
| VHDL_macros\clock_generator_pll_7_to_1_diff_ddr.vhd | 13108 | 2015-01-07
|
| VHDL_macros\clock_generator_pll_7_to_1_diff_sdr.vhd | 11752 | 2015-01-07
|
| VHDL_macros\delay_controller_wrap.vhd | 18719 | 2015-01-07
|
| VHDL_macros\gearbox_4_to_7.vhd | 9052 | 2015-01-07
|
| VHDL_macros\gearbox_4_to_7_slave.vhd | 8188 | 2015-01-07
|
| VHDL_macros\n_x_serdes_1_to_7_mmcm_idelay_ddr.vhd | 15786 | 2015-01-07
|
| VHDL_macros\n_x_serdes_1_to_7_mmcm_idelay_sdr.vhd | 14305 | 2015-01-07
|
| VHDL_macros\n_x_serdes_7_to_1_diff_ddr.vhd | 5907 | 2015-01-07
|
| VHDL_macros\n_x_serdes_7_to_1_diff_sdr.vhd | 5707 | 2015-01-07
|
| VHDL_macros\serdes_1_to_7_mmcm_idelay_ddr.vhd | 37496 | 2015-01-07
|
| VHDL_macros\serdes_1_to_7_mmcm_idelay_sdr.vhd | 29092 | 2015-01-07
|
| VHDL_macros\serdes_1_to_7_slave_idelay_ddr.vhd | 22158 | 2015-01-07
|
| VHDL_macros\serdes_1_to_7_slave_idelay_sdr.vhd | 18599 | 2015-01-07
|
| VHDL_macros\serdes_7_to_1_diff_ddr.vhd | 11369 | 2015-01-07
|
| VHDL_macros\serdes_7_to_1_diff_sdr.vhd | 8137 | 2015-01-07
|
| VHDL_testbench | 0 | 2015-01-08
|
| VHDL_testbench\tb_top5x2_7to1_ddr.vhd | 6075 | 2015-01-07
|
| VHDL_testbench\tb_top5x2_7to1_sdr.vhd | 6072 | 2015-01-07
|
| VHDL_top_level_examples | 0 | 2015-01-08
|
| VHDL_top_level_examples\top5x2_7to1_ddr_rx.vhd | 11142 | 2015-01-07
|
| VHDL_top_level_examples\top5x2_7to1_ddr_tx.vhd | 9857 | 2015-01-07
|
| VHDL_top_level_examples\top5x2_7to1_sdr_rx.vhd | 10690 | 2015-01-07
|
| VHDL_top_level_examples\top5x2_7to1_sdr_tx.vhd | 9321 | 2015-01-07
|
| xapp585_ Uncertainties_ tool_ 1.2.xlsx | 15365 | 2013-10-03
|
| xdc | 0 | 2015-01-08
|
| xdc\top5x2_7to1_ddr_rx.xdc | 8806 | 2015-01-07
|
| xdc\top5x2_7to1_ddr_tx.xdc | 7195 | 2015-01-07
|
| xdc\top5x2_7to1_sdr_rx.xdc | 8440 | 2015-01-07
|
| xdc\top5x2_7to1_sdr_tx.xdc | 7196 | 2015-01-07 |
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