Filename
Size
Date
XAPP1064\readme.txt
 5265 
 2016-02-19
XAPP1064\Verilog_Source
 0 
 2011-03-01
XAPP1064\Verilog_Source\Macros
 0 
 2011-03-01
XAPP1064\Verilog_Source\Macros\clock_generator_ddr_s8_diff.v
 6394 
 2010-02-03
XAPP1064\Verilog_Source\Macros\clock_generator_pll_s16_diff.v
 9051 
 2010-02-03
XAPP1064\Verilog_Source\Macros\clock_generator_pll_s8_diff.v
 9646 
 2010-02-03
XAPP1064\Verilog_Source\Macros\clock_generator_sdr_s8_diff.v
 6166 
 2010-02-19
XAPP1064\Verilog_Source\Macros\phase_detector.v
 10743 
 2011-07-18
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_ddr_s8_diff.v
 8499 
 2012-01-10
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_ddr_s8_se.v
 8367 
 2009-11-27
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_pll_s16_diff.v
 20233 
 2010-08-10
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_pll_s8_diff.v
 19509 
 2010-08-10
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_sdr_s8_diff.v
 4941 
 2010-02-19
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_ddr_s8_diff.v
 10998 
 2010-02-05
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_ddr_s8_se.v
 13594 
 2010-02-17
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_s16_diff.v
 11620 
 2010-05-19
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_s8_diff.v
 11711 
 2010-12-06
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_s8_se.v
 13581 
 2010-12-01
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_ddr_s8_diff.v
 9045 
 2010-02-17
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_ddr_s8_se.v
 8928 
 2010-02-17
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_s16_diff.v
 10667 
 2010-06-22
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_s8_diff.v
 9458 
 2010-06-09
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_s8_se.v
 8854 
 2010-02-17
XAPP1064\Verilog_Source\Top level examples
 0 
 2011-03-01
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR
 0 
 2011-03-01
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\tb_top_nto1_ddr.v
 4669 
 2009-12-08
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_rx.ucf
 428 
 2009-11-16
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_rx.v
 5393 
 2009-12-08
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_tx.ucf
 364 
 2009-11-16
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_tx.v
 5219 
 2009-12-08
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_rx.ucf
 523 
 2009-11-16
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_rx.v
 5351 
 2009-12-08
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_tx.ucf
 256 
 2009-11-16
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_tx.v
 5140 
 2009-12-08
XAPP1064\Verilog_Source\Top level examples\PLL
 0 
 2011-03-01
XAPP1064\Verilog_Source\Top level examples\PLL\tb_top_nto1_pll.v
 4850 
 2009-12-08
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx.ucf
 428 
 2009-11-16
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx.v
 5283 
 2009-11-23
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx_and_tx.ucf
 645 
 2009-11-23
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx_and_tx.v
 6234 
 2009-11-23
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_tx.ucf
 367 
 2009-11-20
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_tx.v
 5182 
 2009-11-23
XAPP1064\Verilog_Source\Top level examples\PLL_16
 0 
 2011-03-01
XAPP1064\Verilog_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx.ucf
 669 
 2010-05-18
XAPP1064\Verilog_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx.v
 5340 
 2010-05-18
XAPP1064\Verilog_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx_and_tx.ucf
 886 
 2010-05-18
XAPP1064\Verilog_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx_and_tx.v
 6022 
 2010-05-18
XAPP1064\Verilog_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_tx.ucf
 546 
 2010-05-18
XAPP1064\Verilog_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_tx.v
 5100 
 2010-05-18
XAPP1064\VHDL_Source
 0 
 2011-03-01
XAPP1064\VHDL_Source\Macros
 0 
 2011-03-01
XAPP1064\VHDL_Source\Macros\clock_generator_ddr_s8_diff.vhd
 6666 
 2010-02-03
XAPP1064\VHDL_Source\Macros\clock_generator_pll_s16_diff.vhd
 9801 
 2010-02-03
XAPP1064\VHDL_Source\Macros\clock_generator_pll_s8_diff.vhd
 10294 
 2010-02-03
XAPP1064\VHDL_Source\Macros\clock_generator_sdr_s8_diff.vhd
 6488 
 2010-02-03
XAPP1064\VHDL_Source\Macros\phase_detector.vhd
 11514 
 2011-04-26
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_clk_ddr_s8_diff.vhd
 6811 
 2012-01-10
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_clk_ddr_s8_se.vhd
 8906 
 2009-12-08
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_clk_pll_s16_diff.vhd
 21780 
 2010-08-10
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_clk_pll_s8_diff.vhd
 20829 
 2010-08-10
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_clk_sdr_s8_diff.vhd
 5071 
 2010-02-19
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_data_ddr_s8_diff.vhd
 13121 
 2012-01-10
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_data_ddr_s8_se.vhd
 15617 
 2010-02-17
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_data_s16_diff.vhd
 13711 
 2010-06-22
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_data_s8_diff.vhd
 13419 
 2010-06-09
XAPP1064\VHDL_Source\Macros\serdes_1_to_n_data_s8_se.vhd
 15493 
 2010-12-01
XAPP1064\VHDL_Source\Macros\serdes_n_to_1_ddr_s8_diff.vhd
 9550 
 2010-02-17
XAPP1064\VHDL_Source\Macros\serdes_n_to_1_ddr_s8_se.vhd
 9464 
 2010-02-17
XAPP1064\VHDL_Source\Macros\serdes_n_to_1_s16_diff.vhd
 12251 
 2010-12-15
XAPP1064\VHDL_Source\Macros\serdes_n_to_1_s8_diff.vhd
 9875 
 2010-06-09
XAPP1064\VHDL_Source\Macros\serdes_n_to_1_s8_diff.vhd.bak
 9769 
 2010-05-22
XAPP1064\VHDL_Source\Macros\serdes_n_to_1_s8_se.vhd
 9376 
 2010-02-17
XAPP1064\VHDL_Source\Top level examples
 0 
 2011-03-01
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR
 0 
 2011-03-01
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\tb_top_nto1_ddr.vhd
 6999 
 2009-12-08
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_rx.ucf
 428 
 2009-11-16
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_rx.vhd
 7684 
 2009-12-08
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_tx.ucf
 364 
 2009-11-16
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_tx.vhd
 7838 
 2009-12-08
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_rx.ucf
 523 
 2009-11-16
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_rx.vhd
 7746 
 2009-12-08
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_tx.ucf
 256 
 2009-11-16
XAPP1064\VHDL_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_tx.vhd
 7600 
 2009-12-08
XAPP1064\VHDL_Source\Top level examples\PLL
 0 
 2011-03-01
XAPP1064\VHDL_Source\Top level examples\PLL\tb_top_nto1_pll.vhd
 6758 
 2009-11-23
XAPP1064\VHDL_Source\Top level examples\PLL\top_nto1_pll_diff_rx.ucf
 428 
 2009-11-16
XAPP1064\VHDL_Source\Top level examples\PLL\top_nto1_pll_diff_rx.vhd
 7960 
 2009-11-20
XAPP1064\VHDL_Source\Top level examples\PLL\top_nto1_pll_diff_rx_and_tx.ucf
 645 
 2009-11-23
XAPP1064\VHDL_Source\Top level examples\PLL\top_nto1_pll_diff_rx_and_tx.vhd
 10131 
 2009-11-23
XAPP1064\VHDL_Source\Top level examples\PLL\top_nto1_pll_diff_tx.ucf
 367 
 2009-11-20
XAPP1064\VHDL_Source\Top level examples\PLL\top_nto1_pll_diff_tx.vhd
 7413 
 2009-11-20
XAPP1064\VHDL_Source\Top level examples\PLL_16
 0 
 2011-03-01
XAPP1064\VHDL_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx.ucf
 669 
 2010-05-18
XAPP1064\VHDL_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx.vhd
 8560 
 2010-05-19
XAPP1064\VHDL_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx_and_tx.ucf
 886 
 2010-05-18
XAPP1064\VHDL_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_rx_and_tx.vhd
 10351 
 2010-05-19
XAPP1064\VHDL_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_tx.ucf
 546 
 2010-05-18
XAPP1064\VHDL_Source\Top level examples\PLL_16\top_nto1_pll_16_diff_tx.vhd
 7545 
 2010-05-19
XAPP1064
 0 
 2012-01-10