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Title: LU Matrix Factorization Download
  • Category:
  • Algorithm
  • Tags:
  • File Size:
  • 1.57mb
  • Update:
  • 2018-03-23
  • Downloads:
  • 0 Times
  • Uploaded by:
  • ayasp
 Description: The realization of N order reversible matrix decomposition on the Xilinx platform using C language
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File list (Check if you may need any files): 
FilenameSizeDate
BasicLU 0  2018-03-23

BasicLU\BasicLU_HLS 0  2018-03-23

BasicLU\BasicLU_HLS\.apc 0  2018-03-23

BasicLU\BasicLU_HLS\.apc\.src 0  2013-03-27

BasicLU\BasicLU_HLS\.apc\.tb 0  2013-03-27

BasicLU\BasicLU_HLS\.apc\autopilot.apfmapping 525  2013-04-04

BasicLU\BasicLU_HLS\.cproject 17957  2013-04-04

BasicLU\BasicLU_HLS\.project 5208  2013-04-04

BasicLU\BasicLU_HLS\.settings 0  2018-03-23

BasicLU\BasicLU_HLS\.settings\BasicLU_HLS.Debug.launch 2110  2013-04-04

BasicLU\BasicLU_HLS\.settings\BasicLU_HLS.Release.launch 2027  2013-04-04

BasicLU\BasicLU_HLS\.vivado_hls_log.xml 16823  2013-03-27

BasicLU\BasicLU_HLS\.vivado_hls_log_all.xml 1268310  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\.tcls 0  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\0_NoDirective.aps 3245  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\0_NoDirective.directive 90  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\0_NoDirective.log 9430  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\csim 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\csim\.lst_opt.tcl 39  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\csim.exe 93780  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\csim.mk 2123  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\Makefile.rules 9248  2012-12-08

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\obj 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\obj\.dir 0  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\obj\InvMatLU.o 38909  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\obj\InvMatLU_tb.o 34056  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\run_sim.tcl 1397  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\build\sim.bat 36  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\csim\report 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\csim\report\InvertMatrix_csim.log 308  2013-03-27

BasicLU\BasicLU_HLS\0_NoDirective\directives.tcl 263  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\script.tcl 555  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\report 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\InvertMatrix_csynth.rpt 11497  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\InvertMatrix_csynth.xml 5418  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\LUDecomp_csynth.rpt 14368  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\LUDecomp_csynth.xml 6899  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\ProductTriangle_csynth.rpt 9829  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\ProductTriangle_csynth.xml 5573  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\TriangleInverse_csynth.rpt 14699  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\report\TriangleInverse_csynth.xml 5824  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ACMP_fadd.h 26  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ACMP_faddfsub.h 26  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ACMP_fdiv.h 26  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ACMP_fmul.h 26  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ACMP_frecip.h 26  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\AESL_comp.h 44246  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\AESL_pkg.h 15674  2013-03-22

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix.cpp 48439  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix.h 10614  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_A.cpp 3292  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_A.h 7784  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_fadd_32ns_32ns_32_10_full_dsp.h 1305  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_faddfsub_32ns_32ns_32_10_full_dsp.h 1455  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_fdiv_32ns_32ns_32_30.h 1269  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_fmul_32ns_32ns_32_7_max_dsp.h 1296  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_frecip_32ns_32ns_32_19_full_dsp.h 1335  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_InvA.cpp 1230  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\InvertMatrix_InvA.h 7188  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\LUDecomp.cpp 80065  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\LUDecomp.h 19153  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ProductTriangle.cpp 28244  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\ProductTriangle.h 7325  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\TriangleInverse.cpp 65214  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\systemc\TriangleInverse.h 16029  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix.v 28406  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_A.v 1795  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_fadd_32ns_32ns_32_10_full_dsp.v 2414  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_faddfsub_32ns_32ns_32_10_full_dsp.v 2792  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_fdiv_32ns_32ns_32_30.v 3736  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_fmul_32ns_32ns_32_7_max_dsp.v 2219  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_frecip_32ns_32ns_32_19_full_dsp.v 2751  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\InvertMatrix_InvA.v 1446  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ips 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ips\fadd_v6.vhd 5739  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ips\faddsub_v6.vhd 6091  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ips\fdiv_v6.vhd 5739  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ips\fmul_v6.vhd 5739  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ips\frecip_v6.vhd 5499  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\LUDecomp.v 56754  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\ProductTriangle.v 16282  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\verilog\TriangleInverse.v 41030  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix.vhd 38371  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_A.vhd 4234  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_fadd_32ns_32ns_32_10_full_dsp.vhd 3989  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_faddfsub_32ns_32ns_32_10_full_dsp.vhd 4617  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_fdiv_32ns_32ns_32_30.vhd 6082  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_fmul_32ns_32ns_32_7_max_dsp.vhd 3675  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_frecip_32ns_32ns_32_19_full_dsp.vhd 4496  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\InvertMatrix_InvA.vhd 3186  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\ips 0  2018-03-23

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\ips\fadd_v6.vhd 5739  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\ips\faddsub_v6.vhd 6091  2013-04-04

BasicLU\BasicLU_HLS\0_NoDirective\syn\vhdl\ips\fdiv_v6.vhd 5739  2013-04-04

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