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Title: 53777 集成电路静态时序分析与建模 Download
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  • Other systems
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  • File Size:
  • 13kb
  • Update:
  • 2019-06-24
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  • Uploaded by:
  • XLLLLLL
 Description: Static Sequence Analysis and Modeling of 53777 Integrated Circuit
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File list (Check if you may need any files):
FilenameSizeDate
提交的资料\eco_fix_violations.tcl 21093 2016-07-16
提交的资料\get_buffers.tcl 4175 2016-07-16
提交的资料\get_failing_paths_high_slew.tcl 3626 2016-07-16
提交的资料\get_interclock_skew.tcl 1428 2016-07-16
提交的资料\get_ports_edge_sense.tcl 5423 2016-07-16
提交的资料\report_clock_endpoint_skew.tcl 6107 2016-07-16
提交的资料\report_unclocked.tcl 1562 2016-07-16
提交的资料\report_violations.tcl 7358 2016-07-16
提交的资料 0 2016-07-16

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