基于FPGA的直接数字合成器设计 a use FLEX10-chip RAM resources,

Title: 基于FPGA的直接数字合成器设计

Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
21.66kb
Update:
2008-10-13
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Uploaded by:
cymail

Description: a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.

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