Description: i2c bus read and write a byte procedures. The written procedure, not necessarily require the detection i2c-response, and can directly past trip delay, but the process must be read to the response signal, stopped at reading, we recognize the signals are on the fat. Otherwise, the address read for the course could not go wrong, but the randomness of the process would be a mistake, I was in the process to stop for no signal, 24cxx in output data, read errors. I discovered the problem after the procedure just joined the order of a completely normal.
File list (Check if you may need any files):
Download