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Title:
bidir
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
3.77kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
skl_download
Description:
Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
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