- Category:
- ISAPI-IE
- Tags:
-
[WORD]
- File Size:
- 81.16kb
- Update:
- 2008-10-13
- Downloads:
- 0 Times
- Uploaded by:
- niezhi
Description: VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
File list (Check if you may need any files):
Download