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[Other resource] 数据选择器vhd源代码

Description: 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
Platform: | Size: 11725 | Author: kljd | Hits:

[Program doc] apb_bridge.vhd

Description: apb_bridge.vhd
Platform: | Size: 1846 | Author: azhe5587 | Hits:

[SourceCode] AHB2APB.vhd

Description: AHB2APB.vhd
Platform: | Size: 5003 | Author: shuli124@163.com | Hits:

[VHDL-FPGA-Verilog] 数据选择器vhd源代码

Description: 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
Platform: | Size: 11264 | Author: kljd | Hits:

[VHDL-FPGA-Verilog] [eda]vhdl

Description: 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）-Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Platform: | Size: 222208 | Author: 林锋杰 | Hits:

[Other Embeded program] vhd

Description: 基于maxplusII的EDA设计，自动绕线机的设计源程序。-maxplusII Based on the EDA design, automatic winding machine design source.
Platform: | Size: 156672 | Author: weini | Hits:

[VHDL-FPGA-Verilog] clock_top2

Description: 数字钟的vhd文档，个人感觉还是蛮完善的，大家可以下载了一同改进。-figures minute vhd files, individuals still feel pretty good, we can improve downloaded together.
Platform: | Size: 2048 | Author: john | Hits:

[VHDL-FPGA-Verilog] multi4

Description: fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
Platform: | Size: 1024 | Author: 杨奎元 | Hits:

[MiddleWare] fftipcore

Description: 该程序是vhdl语言编写的fft变换的ip核代码，程序中共包含了36个.vhd文件-that the procedure was prepared by the vhdl language fft transform ip nuclear code CPC procedures contained 36. vhd documents
Platform: | Size: 29696 | Author: 袁汇 | Hits:

[VHDL-FPGA-Verilog] vhd

Description: 一个VHDL电梯控制器的程序 1、每层电梯的入口处设有上下请求开关，电梯内设有乘客到达层次的停站请求开关。 2、设有电梯所处位置指示装置及电梯运行模式（上升或下降）指示装置。 3、电梯每秒升降一层。 4、电梯到达有停站请求的楼层后，经过1s电梯打开，开门只是灯亮，开门4s后，电梯门关闭（关门指示灯灭），电梯继续运行，直至执行完请求信号后停在当前楼层。 5、能记忆电梯内外的所以请求信号，并按照电梯运行规则依次响应，每个请求信号保留至执行后消除。 6、电梯运行规则：当电梯处于上升模式时，只响应比电梯所在位置高的上楼信号，由下至上依次执行，直到最后一个上楼请求执行完毕，如更高层有下楼请求时，则直接升到有下降请求的最高楼接客，然后进入下降模式，但电梯处于下降模式时，则与上升模式相反。 7、电梯初始状态为一层门开。-err
Platform: | Size: 124928 | Author: | Hits:

[VHDL-FPGA-Verilog] AD9826.vhd

Description: 驱动AD9826的VHDL程序，经测试可以成功驱动-AD9826 driver of VHDL procedures, have been tested successfully drive
Platform: | Size: 1024 | Author: wuchao | Hits:

[VHDL-FPGA-Verilog] PCI-T32

Description: PCI.VHD, THE INTERFACE MODULE WITH PCI AGENT CHIP --v1.0: For CY7C9689, First Version working on L01A chip --V2.0: For simplified PCI Agent, Xilinx and AMD chips
Platform: | Size: 1024 | Author: 7845623 | Hits:

[VHDL-FPGA-Verilog] 13

Description: para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
Platform: | Size: 3072 | Author: libing | Hits:

[Windows Develop] 11

Description: cnt6.bdf 六进制约翰逊计数器 counters.vhd 不同功能的简单计数器 count60.vhd 60进制计数器 count60.bdf 60进制计数器 counter_1024.vhd 8位二进制计数器 counter_1m.vhd 16位二进制计数器 counter.vhd N进制计数器-M Johnson cnt6.bdf six different functions counters.vhd counter simple counter count60.vhd 60 hexadecimal counter count60.bdf 60 hexadecimal counter counter_1024.vhd 8 bit binary counter counter_1m.vhd 16 bit binary counter counter.vhd N M-ary Counter
Platform: | Size: 7168 | Author: libing | Hits:

[VHDL-FPGA-Verilog] pinluji

Description: 四位十进制频率计设计包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 -Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of the original procedure (vhd), waveform file (wmf), packaged components (bsf). Top-level schematic document (Block1.bdf) and waveform.
Platform: | Size: 11264 | Author: 深空 | Hits:

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