Search - 乒乓缓存

[Other resource] pingpang

Description: 实现乒乓缓存，用verilog语言编写！
Platform: | Size: 166585 | Author: zhl | Hits:

[Other resource] VHDL

Description: 高质量的VHDL代码乒乓处理FIFO缓存
Platform: | Size: 915 | Author: wode | Hits:

[VHDL-FPGA-Verilog] 乒乓缓存vhdl代码

Description: 兵乓缓存vhdl代码，用于高速缓存使用
Platform: | Size: 162638 | Author: yangyu141827 | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 实现乒乓缓存，用verilog语言编写！-Realize cache ping-pong, using Verilog language!
Platform: | Size: 165888 | Author: zhl | Hits:

[source in ebook] VHDL

Description: 高质量的VHDL代码乒乓处理FIFO缓存-High-quality VHDL code deal with ping-pong FIFO cache
Platform: | Size: 1024 | Author: wode | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 关于乒乓操作的，对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
Platform: | Size: 166912 | Author: 敬亮 | Hits:

[VHDL-FPGA-Verilog] ping_pong_buffer

Description: 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
Platform: | Size: 36864 | Author: 小强 | Hits:

[Other] DSP

Description: 高速DSP图像处理系统中的乒乓缓存结构研究-Ping-pong cache structure research in high-speed DSP image processing system
Platform: | Size: 212992 | Author: Li | Hits:

[Internet-Network] Net-capture-code

Description: 用于捕获网口数据包的源代码,采用乒乓缓存方式和多线程的方式实现，高效可行-it is use to capture net data packet!
Platform: | Size: 9216 | Author: Hunter Chen | Hits:

[VHDL-FPGA-Verilog] pingpong_operation_FIFO

Description: 通过fifo实现乒乓操作的功能，具有数据缓存的作用，特别适用于高低速的数据传输-Ping-pong operation realized by fifo function has the effect of data cache, especially suitable for high speed data transmission
Platform: | Size: 1906688 | Author: 钟朗朗 | Hits:

[SCM] webPlayer

Description: 第一个版本的原型机会采用Cortex M3级别的芯片，使用SD卡作为音乐的缓冲区，通过WiFi模块配合 lwIP网络协议栈连接豆瓣服务器，将数据首先下载到SD卡中缓存起来；系统采用一块Vx10xx MP3解码芯片实现音乐的解码和播放。播放模块始终从SD卡中读取缓存的音乐，从而避免由于网络不稳定带来的糟糕的播放体验。为了保护该开源项目，SD卡将不使用任何标准的文件系统，我们会将其视作一个巨大的FLASH缓冲区使用，配合一个简单的链表式存储结构来保存和索引音乐文件。为了解决TCP下载音乐到SD卡以及从SD进行音乐播放时产生的读写冲突，我们引入了两个SPI Flash作为中间的乒乓双缓冲介质。该版本使用改进的xmodem协议进行简单的流控制，通过超级终端播放（下载）MP3文件到系统进行缓冲，并由系统发送到Vx10xx模块。-The first version of the prototype using Cortex M3 level of the chip, using the SD card as a buffer with music, through the WiFi module LwIP network protocol stack connection bean server, data will be downloaded to the SD card in the first cache the system uses a Vx10xx MP3 decoder Chip realization of decoding and playing music. Playing module always read cache the music in the SD card, so as to avoid network instability brought Bad playback experience. In order to protect the open source project, SD card file system will not use any standard, we will regard it as a great The use of FLASH buffer, with a simple linked list storage structure to store and index the music file. In order to solve the TCP Download Music To the SD card and the SD to play music is produced when the read-write conflict, we introduce two SPI Flash as the middle of the table tennis double buffer medium. The version of the simple flow control using the improved XMODEM protocol, playing through the super te
Platform: | Size: 1058816 | Author: 大鹏集成 | Hits:

[Other] NandBuffer

Description: verilog编写，含三路正弦信号发生器，三路数据乒乓缓存模块。乒乓缓存读写控制采用三段式状态机实现。-The project contains a 3-channel sine generator and a 3-channel ping-pong buffer which is written in verilog. The write and read control of buffer is implemented in 3-segment FSM.
Platform: | Size: 8192 | Author: shanhuancui | Hits:

[VHDL-FPGA-Verilog] PingPang_buffer_20160526

Description: 源码仿真乒乓缓存，实现数据流的传输，含有仿真测试文件，vivado工程。-Source simulation ping-pong cache data stream transmission, the file containing the simulation test, vivado project.
Platform: | Size: 2422784 | Author: 贾俊超 | Hits:

[Other] intr_priority_control

Description: 多种数据缓存ddr3，乒乓缓存优先级判断，优先将缓存紧急的数据类型读出ddr3.(A variety of data cache DDR3, table tennis cache priority judgment, priority will cache urgent data type read ddr3.)
Platform: | Size: 2048 | Author: huwei6697 | Hits:

[VHDL-FPGA-Verilog] uart_test

Description: 收发端都采用2M波特率发送串口数据，通过PIN口直接输入输出串口数据，目的是为了跟外围高速器件完成高速的串口数据的收发，普通USB转串口的都只能支持不到1M的波特率，内部采用乒乓FIFO进行时钟域切换以及缓存(The transmitter and receiver are used 2M baud rate serial data transmission, directly through the PIN port serial input and output data, the purpose is to complete the serial data with peripheral devices of high-speed high-speed transceiver, USB serial general can only support to 1M baud rate, internal use of table tennis for FIFO clock domain switching and cache)
Platform: | Size: 16316416 | Author: marktuwen | Hits:

[VHDL-FPGA-Verilog] PPRAM-test

Description: 乒乓缓存，用vhdl编写，用fpga内部ram(Ping-pong buffer, using vhdl to write,)
Platform: | Size: 8834048 | Author: 任天鹏 | Hits:

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[Other resource] pingpang

[Other resource] VHDL

[VHDL-FPGA-Verilog] 乒乓缓存vhdl代码

[VHDL-FPGA-Verilog] pingpang

[source in ebook] VHDL

[VHDL-FPGA-Verilog] pingpang

[VHDL-FPGA-Verilog] ping_pong_buffer

[Other] DSP

[Internet-Network] Net-capture-code

[VHDL-FPGA-Verilog] pingpong_operation_FIFO

[SCM] webPlayer

[Other] NandBuffer

[VHDL-FPGA-Verilog] PingPang_buffer_20160526

[Other] intr_priority_control

[VHDL-FPGA-Verilog] uart_test

[VHDL-FPGA-Verilog] PPRAM-test

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