Search - 译码器

[Other resource] 译码器

Description: 通过对用硬件描述语言VHDL表示的某个专用部件（如中断控制器、差错控制码编码/译码器，此为译码器）的代码分析，构建它的逻辑结构，加深对相关部件设计技术的理解。试验平台：MaxPlusII -through the use of VHDL hardware description language said a special components (such as interrupt controllers, error control coding / decoding devices, such as decoder) code analysis, building its logical structure, deepen the relevant parts design technology understanding. Test Platform : MaxPlusII
Platform: | Size: 30156 | Author: johnmad | Hits:

[Other resource] 一些译码器源代码

Description: 内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
Platform: | Size: 3903 | Author: 蔡孟颖 | Hits:

[Web Server] 哈夫曼编译码器

Description: 用C语言写的哈夫曼编译码器-C language written Huffman Decoder
Platform: | Size: 1598 | Author: 连 | Hits:

[Technology Management] RS编译码器的DSP实现

Description:

RS编译码器的DSP实现,首先是MATLAB编程，然后是DSP实现

Platform: | Size: 864936 | Author: xiaofan308 | Hits:

[Documents] 哈夫曼编/译码器课程设计

Description: 利用哈夫曼编码进行信息通讯可以大大提高信道利用率，缩短信息传输时间，降低传输成本。但是，这要求在发送端通过一个编码系统对待传数据预先编码，在接收端将传来的数据进行译码（复原）。对于双工信道（即可以双向传输信息的信道），每端都需要一个完整的编/译码系统。试为这样的信息收发站写一个哈夫曼码的编译码系统基本要求： 1.接收原始数据：从终端读入字符集大小n,n个字符和n个权值，建立哈夫曼树 2.编码：利用已建好的哈夫曼树，对文件中的正文进行编码 3.译码：利用已建好的哈夫曼树将代码进行译码. ...
Platform: | Size: 6934 | Author: jianshengzhijian@126.com | Hits:

[VHDL-FPGA-Verilog] VHDL语言实现3—8译码器

Description: 应用VHDL语言编写的3—8译码器，简单易懂
Platform: | Size: 9661 | Author: 521feijiepeng@163.com | Hits:

[WEB Code] 哈夫曼编译码器

Description: 用C语言写的哈夫曼编译码器-C language written Huffman Decoder
Platform: | Size: 1024 | Author: 连 | Hits:

[VHDL-FPGA-Verilog] 3-8译码器

Description: vhdl的3-8译码器-instantiate the 3-8 decoder
Platform: | Size: 999424 | Author: 熊辉波 | Hits:

[Data structs] Hfmtree编译码器

Description: 利用哈夫曼编码进行通信可以大大提高通信信道利用率，缩短信息传输时间，降低传输成本。这要求在发送端通过一个编码系统将传输数据预先编码；在接收端将传来的数据进行译码（复原）。对于双工信道（即可以双工传输信息的信道），每端都需要一个完整的编/译码系统。为这样的信息收发站设计的一个哈夫曼编/译码系统。-use Huffman coding communication can greatly enhance communication channel utilization, reduced transmission time, and lower transmission costs. This requires the transmitter through a coding system will transmit data in advance coding; The receiving end of the data came decoding (recovery). For dual-channel (that is, information can duplex transmission channel), each side needs a complete encoding/decoding system. For this information hubs designed a Huffman encoding/decoding system.
Platform: | Size: 2048 | Author: cuckoo | Hits:

[VHDL-FPGA-Verilog] 译码器

Description: 通过对用硬件描述语言VHDL表示的某个专用部件（如中断控制器、差错控制码编码/译码器，此为译码器）的代码分析，构建它的逻辑结构，加深对相关部件设计技术的理解。试验平台：MaxPlusII -through the use of VHDL hardware description language said a special components (such as interrupt controllers, error control coding/decoding devices, such as decoder) code analysis, building its logical structure, deepen the relevant parts design technology understanding. Test Platform : MaxPlusII
Platform: | Size: 29696 | Author: johnmad | Hits:

[VHDL-FPGA-Verilog] 一些译码器源代码

[SCM] 5、译码器实验

Description: 这是单片机中的译码器实验程序，仅供初学者学习和使用。(This is a singlechip decoder experimental procedures for beginners to learn and use.)
Platform: | Size: 1394688 | Author: 大偶 | Hits:

[VHDL-FPGA-Verilog] decoder38-ok-38译码器

Description: 使用quartus2软件的VHDL编写了简单38译码器，希望大家能积极学习(The use of quartus2 software VHDL prepared a simple 38 decoder, I hope we can actively study)
Platform: | Size: 109568 | Author: wangwei894535358 | Hits:

[Embeded-SCM Develop] 动态数码管（带译码器）程序

Description: 动态数码管（带译码器）的全部源程序。分为各个模块。(Dynamic digital tube (with decoder) of all source code. It is divided into modules.)
Platform: | Size: 15360 | Author: 浮梦浅宸 | Hits:

[Embeded-SCM Develop] 动态数码管（不带译码器）程序

Description: 本文档包含了动态数码管（不带译码器）的所有源程序，分为各个模块。(This document contains all the source code of the dynamic digital tube (without the decoder), and is divided into modules.)
Platform: | Size: 15360 | Author: 浮梦浅宸 | Hits:

[Software Engineering] 3-8译码器

Description: 基于vhdl的3-8译码器的代码输入、测试平台及仿真(Code input of 3-8 decoders)
Platform: | Size: 1024 | Author: 莫小依 | Hits:

[VHDL-FPGA-Verilog] 74HC4511 7段显示译码器

Description: 译码器，七段显示译码器，内含波形图，测试代码和源码，以及.v文件，verilog编写，ise平台运行(Decoder, seven segment display decoder, contain waveform, test code and source code, as well as.V file, Verilog writing, ISE platform running)
Platform: | Size: 190464 | Author: doubleOlive | Hits:

[VHDL-FPGA-Verilog] 3-8译码器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination of the 3-8 decoder logic device)
Platform: | Size: 10240 | Author: lixilin | Hits:

[Data structs] 哈夫曼编码器，译码器问题

Description: 完成哈夫曼编码，译码问题，用C语言实现编码器，译码器的功能。(Complete the Hoffman code, decoding the problem, using the C language to implement the encoder, decoder functions.)
Platform: | Size: 314368 | Author: 朱达 | Hits:

[VHDL-FPGA-Verilog] RS(204,188)译码器的设计

Description: RS(204,188)译码器说明原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。仿真波形： rs_decoder.vwf。(RS (204188) decoder explanation Original document: Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations). Forney.v (Forney algorithm for error sample), CheinSearch.v (search wrong location), ff_mul.v (finite field multiplication). ROM and initialization files: Rom_inv.v (inverse operation), rom_power.v (exponentiation operation). Rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization file). Simulation waveform: Rs_decoder.vwf.)
Platform: | Size: 15360 | Author: HelloFrank0 | Hits:

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