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[Other resource] 除法器

Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
Platform: | Size: 50091 | Author: johnmad | Hits:

[Other] 1.7运算器部件实验：除法器

Description: 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
Platform: | Size: 152080 | Author: 李乐雅 | Hits:

[Other] fpdiv_vhdl四位除法器

Description: fpdiv_vhdl四位除法器 -- DESCRIPTION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high-fpdiv_vhdl four divider -- DESCRIPTION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high
Platform: | Size: 983 | Author: 张洪 | Hits:

[Other resource] vhdl实现除法器

Description: vhdl实现除法器
Platform: | Size: 1050 | Author: sunchao1228 | Hits:

[Windows Develop] div2 32位除法器

Description: ：32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32
Platform: | Size: 1532 | Author: hyh110120119@163.com | Hits:

[SourceCode] VHDL除法器

Description: 用vhdl实现除法器，很好用，经过验证!
Platform: | Size: 50230 | Author: 568895323@qq.com | Hits:

[SourceCode] 除法器verilog

Description: 32位除法器，verilog编写
Platform: | Size: 1532 | Author: mhdmhdys@126.com | Hits:

[VHDL-FPGA-Verilog] fpdiv_vhdl

Description: 四位除法器的VHDL源程序-four division of VHDL source
Platform: | Size: 1024 | Author: 张庆辉 | Hits:

[VHDL-FPGA-Verilog] 除法器

Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
Platform: | Size: 50176 | Author: johnmad | Hits:

[ISAPI-IE] subr

Description: VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。 其实现方法是，将除法器分为两个状态：等待状态与运算状态。 开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Platform: | Size: 82944 | Author: aa | Hits:

[VHDL-FPGA-Verilog] 数字系统设计教程4_9

Description: vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
Platform: | Size: 244736 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] 数字系统设计相关

Description: 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
Platform: | Size: 45056 | Author: 刘建 | Hits:

[Other] 1.7运算器部件实验：除法器

Description: 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
Platform: | Size: 151552 | Author: 李乐雅 | Hits:

[Other] fpdiv_vhdl四位除法器

Description: fpdiv_vhdl四位除法器 -- DESCRIPTION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high-fpdiv_vhdl four divider-- DESCRIPTION : Signed divider-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 4-- DIV_BY_0 (DIVz) output active : high
Platform: | Size: 1024 | Author: 张洪 | Hits:

[Other] DIVIDER

Description: 除法器，这是一个简单的除法器，虽然位数不是很长，但是可以通过这个程序延伸-divider, which is a simple divider, while the median is not very long, but it extends through this procedure
Platform: | Size: 1024 | Author: 田晓雷 | Hits:

[VHDL-FPGA-Verilog] VHDL5

Description: 加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
Platform: | Size: 6144 | Author: | Hits:

[VHDL-FPGA-Verilog] fixed_pointDivider

Description: 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
Platform: | Size: 397312 | Author: litao | Hits:

[Algorithm] divider1

Description: FPGA 除法器程序-FPGA divider procedures
Platform: | Size: 1024 | Author: | Hits:

[Documents] changyongdevhdl

Description: 4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态 机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the cases of design, the highest priority encoder
Platform: | Size: 11264 | Author: 刘思雄 | Hits:

[MPI] arban

Description: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Platform: | Size: 1024 | Author: arban | Hits:
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