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[SCM] sin

Description: 以SPCE061A单片机为核心，通过DDS合成技术设计制作了一个步进值能任意调节的多功能信号源。该信号源在1KHz～10MHz范围能输出稳定可调的正弦波，并具有AM、FM、ASK和PSK等调制功能。信号输出部分采用低损耗电流反馈型宽带运放作电压放大，很好地解决了带宽和带负载能力的要求。系统带中文显示和键盘控制功能，操作简便，实现效果良好。-SPCE061A can preview and so on 片 Lennon为， Center Services Toru DDS magnetic rude summarized chirpy术instance, a few leftover制brazing stamp festival值vehicles Qin Kui 任 comment slander people cavity features信ulcers ulcers信Tai Tai 。 clams Now 1KHz `10MHz Kui Yu围HUAI embankment稳corner cavity strip Qin Shu Hao ，弦bleed at the nose of sweet seized AM) FM) ASK Core inflation PSK Tan制features 。信ulcers HUAI snapped embankment Qun Xu malaria tablets using delicious cream changchu destroyed sneeze型compliance turbulent changchu压brazing temperature side of bridge ， exhaust temperature submerged low-hua chiao suspect left Rui turbulent turbulent compliance pupa Xikui weak potato cavity lynx 求。 department turbulent conduct anti中striped text显Rui-ying制satirical features captured ，， Fuzeng brazing Canals Xi现invalid wife of mother
Platform: | Size: 346112 | Author: 郑坤 | Hits:

[VHDL-FPGA-Verilog] cordic_3

Description: 流水线结构的cordic，可以输出sin/cos-Pipelined structure cordic, can output sin/cos
Platform: | Size: 1024 | Author: zq | Hits:

[assembly language] sin

Description: 正弦波。大家看一下请指正-Sine wave. Members to see, please correct me
Platform: | Size: 1024 | Author: 张旭 | Hits:

[VHDL-FPGA-Verilog] Sin_wave

Description: sin波形信号发生起的程序 VHDL语言描述 QUartus-sin waveform signal from the procedure described in VHDL language Quartus
Platform: | Size: 483328 | Author: luyingc | Hits:

[AI-NN-PR] work

Description: 根据解空间的维数可以将优化问题分为一维空间优化和多元优化问题。本程序以求函数：f(x)=x+10*sin(5x)+7*cos(4x),0=<x<=9为例说明遗传算法的源程序-According to the dimension of solution space optimization problem can be divided into one-dimensional space optimization and multi-optimization problem. This procedure in order to function: f (x) = x+ 10* sin (5x)+ 7* cos (4x), 0 =
Platform: | Size: 8192 | Author: lizhizheng | Hits:

[VHDL-FPGA-Verilog] sinfunction

Description: 用cordic算法实现超越函数,sin,cos用此方法也可以实现其他的sinhx,coshx,ex.代码用verilog编写-CORDIC algorithm with transcendental function, sin, cos by this method can also realize other sinhx, coshx, ex. Verilog code used to prepare
Platform: | Size: 236544 | Author: yu_leo | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Platform: | Size: 2529280 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[Other] 0832program(sin-data)

Description: 单片机外围模数转换模块编程，正弦波输出，调试成功-Singlechip external analog-digital conversion module programming, sine wave output, debugging success
Platform: | Size: 1024 | Author: 黄山 | Hits:

[VHDL-FPGA-Verilog] SIN

Description: 使用VHDL语言和CPLD芯片生成39KHz的信号-The use of VHDL language and CPLD chip 39KHz signal generated
Platform: | Size: 219136 | Author: Beyond | Hits:

[VHDL-FPGA-Verilog] tSinCordic

Description: 是codic算法实现Sin的浮点C程序，包括定点和浮点程序，已经通过验证.-Sin is codic floating-point algorithm C procedures, including fixed-point and floating-point procedures, has been validated.
Platform: | Size: 5120 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] sin.tar

Description: 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:

[ELanguage] sin

Description: 正弦信号发生器源文件实现正弦信号发生器，非常有用，欢迎下载。-Sinusoidal signal generator source file achieve sinusoidal signal generator, very useful and welcome to download.
Platform: | Size: 1024 | Author: lee | Hits:

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[SCM] sin

[VHDL-FPGA-Verilog] cordic_3

[assembly language] sin

[VHDL-FPGA-Verilog] Sin_wave

[AI-NN-PR] work

[VHDL-FPGA-Verilog] sinfunction

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[Other] 0832program(sin-data)

[VHDL-FPGA-Verilog] SIN

[VHDL-FPGA-Verilog] tSinCordic

[VHDL-FPGA-Verilog] sin.tar

[ELanguage] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] vhdl_source

[assembly language] sin

[VHDL-FPGA-Verilog] sin

[Other Embeded program] sin

[VHDL-FPGA-Verilog] SIN

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