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[Windows Develop1002016p_Sa_5

Description: 用VHDL语言实现8位十进制计数器的设计,计数结果用实验板上8个数码管显示
Platform: | Size: 54258 | Author: chenli | Hits:

[VHDL-FPGA-Verilog1002016p_Sa_5

Description: 用VHDL语言实现8位十进制计数器的设计,计数结果用实验板上8个数码管显示-VHDL language with eight decimal realize the design of counters, counting the results of experiments on-board with 8 digital tube display
Platform: | Size: 54272 | Author: chenli | Hits:

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