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[Crack Hack] AES算法完整源码

Description: AES算法完整源码-AES complete source
Platform: | Size: 225280 | Author: 天上人间 | Hits:

[Crack Hack] aes_crypto_core_latest.tar

Description: Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
Platform: | Size: 961536 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] aes

Description: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Platform: | Size: 87040 | Author: dinxj | Hits:

[Crack Hack] aes_thesis_v1.0

Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Platform: | Size: 386048 | Author: 蕭嵎之 | Hits:

[Crack Hack] AES_verilog

Description: AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
Platform: | Size: 79872 | Author: 刘蕊丽 | Hits:

[Other] aes_inv_cipher_top

Description: aes ip core, 128 bits
Platform: | Size: 12288 | Author: lai | Hits:

[Crack Hack] LIP1611CORE_AES128_SEC_UWB

Description: AES 128 Synthesisable RTL code
Platform: | Size: 5584896 | Author: jc | Hits:

[VHDL-FPGA-Verilog] FPGA_128_AES_decryption

Description: 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
Platform: | Size: 17012736 | Author: Vlog | Hits:

[VHDL-FPGA-Verilog] aes

Description: verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
Platform: | Size: 7168 | Author: xie | Hits:

[MPI] aes128-bit

Description: vhdl code for aes 128 bit
Platform: | Size: 6144 | Author: MANI | Hits:

[VHDL-FPGA-Verilog] Coding Files

Description: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process.
Platform: | Size: 27648 | Author: kutti | Hits:

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