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[Streaming Mpeg4] sadct

Description: adi 汇编写的2维FDCT程序,分成两个1D-DCT,每个1D-DCT 使用12次乘法和32次加法-Sa'adi compilation of the two-dimensional writing FDCT procedures, divided into two 1D - DCT. Each one D-12 DCT use multiplication and 32 Adder
Platform: | Size: 38531 | Author: tohope | Hits:

[VHDL-FPGA-Verilog] DCT_vhdl

Description: IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesizable
Platform: | Size: 10240 | Author: 陈朋 | Hits:

[Streaming Mpeg4] sadct

Description: adi 汇编写的2维FDCT程序,分成两个1D-DCT,每个1D-DCT 使用12次乘法和32次加法-Sa'adi compilation of the two-dimensional writing FDCT procedures, divided into two 1D- DCT. Each one D-12 DCT use multiplication and 32 Adder
Platform: | Size: 37888 | Author: tohope | Hits:

[DSP program] 1D-DCT

Description: 一个完整的基于DSP的一维DCT变换和逆变换的程序。-A complete DSP-based one-dimensional DCT transform and inverse transform process.
Platform: | Size: 1024 | Author: 张贝贝 | Hits:

[Wavelet] codes

Description: 快速3d离散小波变化，其中1d小波变换函数也进行了改进-fast 3d DCT , where 1d dct is also improved
Platform: | Size: 1330176 | Author: meizi | Hits:

[VHDL-FPGA-Verilog] 1DCT_VHDL

Description: VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.
Platform: | Size: 11264 | Author: NULL | Hits:

[VHDL-FPGA-Verilog] dct

Description: all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
Platform: | Size: 1024 | Author: haziq36 | Hits:

[Picture Viewer] jpeg2bmp

Description: jpeg 解码的快速算法实现， 采用1d的dct实现2ddct-the jpeg decode fast algorithm using 1d the dct to achieve 2ddct
Platform: | Size: 2048 | Author: oliver | Hits:

[VHDL-FPGA-Verilog] shift_arr

Description: This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.
Platform: | Size: 2048 | Author: Prashanth | Hits:

[Wavelet] experiment3

Description: 自编1d数字信号的频域分析，包含FFT/DCT等，是经典的课程实验程序-Frequency domain analysis self 1d digital signal, including FFT/DCT, is a classic course experimental procedure
Platform: | Size: 1024 | Author: 田甜 | Hits:

[Software Engineering] 2D-DCTVERILOG

Description: 2D DCT VERILOG CODE WITH TESTBENCH WHICH HAVING 1D DCT TRANSPOSE MATRIX
Platform: | Size: 31744 | Author: peddinti.rajasekhar | Hits:

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