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[Other resource] 1PPS

Description: 应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发
Platform: | Size: 34954 | Author: 党晓圆 | Hits:

[VHDL-FPGA-Verilog] gps_jiance

Description: 合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
Platform: | Size: 1024 | Author: 远方 | Hits:

[VHDL-FPGA-Verilog] 1PPS

Description: 应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发-Application of VHDL language high stability crystal oscillator frequency to be 1pps, the use of GPS signals as a trigger of 1pps
Platform: | Size: 34816 | Author: 党晓圆 | Hits:

[Program doc] A-Simulation-System-for-Multi-Mobile-Events-in-WS

Description: Sensor networks are a sensing, computing and communication infrastructure that are able to observe and respond to phenomena in the natural environment and in our physical and cyber infrastructure. In this paper, we investigate how the sensor network performs in the case when three events move with special movement path. We compare the simulation results for three cases: stationary, random and simple 4 path. We found that the goodput of random model has the best value among the three models when Tr < 1pps. The average packet loss of simple 4 point model is the lowest among the three models. The RE of stationary model, simple 4 point model and random model has stable values. In case of random model, the RE is better than other models.
Platform: | Size: 285696 | Author: Mohamed Rias | Hits:

[VHDL-FPGA-Verilog] B-decoder1

Description: IRIG-B码的解码以及数码管显示程序，且输出1PPS信号-IRIG-B decoder program in c language,and display in segment.
Platform: | Size: 2048 | Author: liu dacheng | Hits:

[Software Engineering] IRIG-Bcode

Description: 本课题主要研究IRIG-B码的解码过程，并设计一个IRIG-B码的解码装置，使其能够解调出来1pps 标准秒脉冲信号-The main subject of research IRIG-B code decoding process, and to design an IRIG-B code decoding apparatus, so that it can demodulate out 1pps standard second pulse signal
Platform: | Size: 114688 | Author: wangwei | Hits:

[Software Engineering] Signal-1MHz-1pps

Description: 实现分频处理的一个模块。从输出的1MHz信号转化为1pps信号。-Achieve sub-frequency processing module. From the 1MHz signal output into 1pps signal.
Platform: | Size: 1024 | Author: 马总 | Hits:

[Other Embeded program] Stm32_2USART

Description: 使用STM32(cortex-M3核)模拟GPS模块（摩托罗拉产品GT-UT ONCORE）与基站设备交换机通过双串口进行AT指令交互完成授时(cpu之systick产生1pps信号)，测试成功。-Use STM32 (cortex-M3 core) simulated GPS module (Motorola products GT-UT ONCORE) and base station equipment switches through dual serial AT commands interactively complete timing (cpu' s systick produce 1pps signal), the test was successful.
Platform: | Size: 2135040 | Author: 风之魂 | Hits:

[Com Port] main

Description: 对gps的1pps信号进行平滑滤波处理，然后驯服恒温晶振，得到原子钟级稳定度的信号。-1PPS on GPS signals are filtered and then tamed OCXO, get the signal level stability of atomic clock.
Platform: | Size: 2048 | Author: suzhangzhan | Hits:

[SCM] GPS-arm-keil

Description: GPS同步时钟，并利用GPS模块的1PPS秒脉冲定时输出一个开关量-GPS synchronized clock, and the use of GPS module 1PPS timing output a second pulse switch
Platform: | Size: 1623040 | Author: 天蓝 | Hits:

[GPS develop] stm32f0_gpsdo

Description: this is GPS disciplined oscillator source code, based on 1PPS GPS signal and NMEA protocol
Platform: | Size: 1581056 | Author: tipok | Hits:

[VHDL-FPGA-Verilog] pps_ketiao_rb2

Description: FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
Platform: | Size: 7772160 | Author: 张媛 | Hits:

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