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[Other resource] mcu1859

Description: ADSP-BF53x是主频高达600 MHz 高性能Blackfin处理器内核包括：2个16位MAC，2个40位ALU，4个8位视频ALU，以及1个40位移位器 -ADSP-BF53x frequency is as high as 600 MHz with high-performance Blackfin Processor Nuclear include : two MAC 16, two 40 ALU, four 8 Video ALU, and a 40-bit shift device
Platform: | Size: 959581 | Author: shijinfen | Hits:

[MPI] 类sc

Description: 该文件以systemc为核心建立了32位alu，仅供参考-the document to SystemC as the core, a 32-bit ALU, is for reference only
Platform: | Size: 1302528 | Author: asao | Hits:

[Other] mcu1859

Description: ADSP-BF53x是主频高达600 MHz 高性能Blackfin处理器内核包括：2个16位MAC，2个40位ALU，4个8位视频ALU，以及1个40位移位器 -ADSP-BF53x frequency is as high as 600 MHz with high-performance Blackfin Processor Nuclear include : two MAC 16, two 40 ALU, four 8 Video ALU, and a 40-bit shift device
Platform: | Size: 959488 | Author: shijinfen | Hits:

[Software Engineering] 07302529

Description: 计算机组成原理实验（MAX PLUS） 1.ALU设计 2.MEM设计 3.32位2选1选择器-Principles of Computer Organization Experiment (MAX PLUS) 1.ALU design 2.MEM design 3.32 2 election 1 selector
Platform: | Size: 244736 | Author: 翁浩达 | Hits:

[Windows Develop] ALU-FP

Description: ALU floating point 8 bit
Platform: | Size: 781312 | Author: nicola | Hits:

[VHDL-FPGA-Verilog] yetert

Description: This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
Platform: | Size: 458752 | Author: crion | Hits:

[VHDL-FPGA-Verilog] 2bit_ALU

Description: This is a source code of 2 bit ALU and this is in VHDL form.-This is a source code of 2 bit ALU and this is in VHDL form.
Platform: | Size: 2048 | Author: alokesh mondal | Hits:

[VHDL-FPGA-Verilog] slice

Description: A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually internal to the CPU.For example,two 4-bit ALUs could be arranged side by side,with control lines between them,to form an 8-bit ALU.Asequencer executes a program to provide data and control signals.Slice construction conceptually proceeds in two phases.(1) detecting the slice, and (2)extracting the instructions for storage in the slice cache.Detection is done by propagating a dependance vector or DV as follows:Starting from the candidate load send its DV to the immediate preceding slicer entry.Entry checks the bit of the incoming DV .Because it is zero,it just propagates the DV as is to entry 8-A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually internal to the CPU.For example,two 4-bit ALUs could be arranged side by side,with control lines between them,to form an 8-bit ALU.Asequencer executes a program to provide data and control signals.Slice construction conceptually proceeds in two phases.(1) detecting the slice, and (2)extracting the instructions for storage in the slice cache.Detection is done by propagating a dependance vector or DV as follows:Starting from the candidate load send its DV to the immediate preceding slicer entry.Entry checks the bit of the incoming DV .Because it is zero,it just propagates the DV as is to entry 8
Platform: | Size: 1024 | Author: gopan | Hits:

[VHDL-FPGA-Verilog] Code-ALU16BIT

Description: Code ALU 8 bit vhdl arith and logic
Platform: | Size: 994304 | Author: ductuyenxp | Hits:

[VHDL-FPGA-Verilog] MIPS-Parts

Description: // * Data Memory and IO: This is the data memory, and some IO hardware // * 8x16 register file: eight 16-bit registers // * 16-bit ALU // * 2:1 16-bit Multiplexer // * Sign extender from 7 to 16 bits // * 4:1 16-bit Multiplexer-// * Data Memory and IO: This is the data memory, and some IO hardware // * 8x16 register file: eight 16-bit registers // * 16-bit ALU // * 2:1 16-bit Multiplexer // * Sign extender from 7 to 16 bits // * 4:1 16-bit Multiplexer
Platform: | Size: 2048 | Author: Billy Bob | Hits:

[VHDL-FPGA-Verilog] tmr

Description: triple modular redundancy. for 32 bit alu
Platform: | Size: 371712 | Author: neeha | Hits:

[Software Engineering] ALU16bit

Description: design ALU 16 bit in VHDL
Platform: | Size: 349184 | Author: vinh | Hits:

[VHDL-FPGA-Verilog] alu

Description: An ALU with two inputs a and b and four basic ALU functions: output=a+1 or a+b+1 or b or a+b. Using a 2 bit input "sel" to select one function.
Platform: | Size: 1024 | Author: cry | Hits:

[Other Embeded program] VHDL_book2

Description: add4a：4位加法器的设计 add8a：8位加法器的设计 subtract：4位减法器的设计 addsub： 4位加法器/减法器的设计 shift4：移位寄存器的设计 mult4：乘法器设计 div8：除法器设计 alu4：算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit adder/subtractor design shift4: shift register design mult4: Multiplier div8: Divide Design alu4: arithmetic logic unit ALU design
Platform: | Size: 3258368 | Author: 贾诩 | Hits:

[Industry research] ALU_8bit

Description: this is my code for ALU 8 bit
Platform: | Size: 91136 | Author: nguyen | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog code for 8 bit alu
Platform: | Size: 442368 | Author: kumar | Hits:

[VHDL-FPGA-Verilog] ALU-Design

Description: 8 bit alu design features: optimized design inclusive of multiplier
Platform: | Size: 1043456 | Author: Ashutosh | Hits:

[Other] vhdsl_4bit_alu

Description: a 4 BIT alu implemented using vhdl as core language. Works fine on spartan 3e. tested and verified
Platform: | Size: 2437120 | Author: porter | Hits:

[Windows Develop] ALU-master

Description: alu 4 bit, add, sub, com(Perform basic operations, addition, subtraction, comparison)
Platform: | Size: 2048 | Author: tiendat | Hits:

[SCM] US100&sr06热卖超声波资料

Description: //TDC中断输出脚，此脚用要来内配己完成信息的中断提示 //中断引脚Pin8,INT可以有不同的中断源，在寄存器2的Bits29-31（EN_INT）以及寄存器6 //bit 21位中进行选择. //Reg 2 bit 29 = 1 ALU 已经准备好 //Reg 2 bit 30 = 1 被设置的脉冲个数全部被接收到 //Reg 2 bit 31 = 1 TDC 测量单元溢出 //Reg 6 bit 21 = 1 EEPROM 动作的结束 //如果需要两个或两个以上的中断源，可通过“或”门连接不同的选项。 在本章后面将会对 //此设置有更进一步的描述。 //进行了设置之后，用户必须通过发送代码“Init”初始化GP22 以便 TDC 能够接受 Start //和 Stop 信号.(//TDC interrupt output pin, this foot is used to match the completion of their own interrupt information prompts / / interrupt pin Pin8, INT can have different interrupt sources in the Bits29-31 register 2 (EN_INT) and register 6 Select in //bit 21 bit //Reg 2 bit 29 = 1 ALU is ready //Reg 2 bit 30 = 1 the number of pulses being set is all received //Reg 2 bit 31 = 1 TDC measurement unit overflow //Reg 6 bit 21 = 1 EEPROM action ends / / if two or more than two interrupt sources can be connected through different options or gate. It's going to be right behind this chapter This setting / / further description. / / after this is set, the user must be sent through the "Init" code to initialize the GP22 so that TDC can accept Start / / and Stop signals.)
Platform: | Size: 246784 | Author: 韦水伊 | Hits:
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