Description: Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. Introduction to use the environment: Quartus II 7.2 SP1+ DE2 (Cyclone II EP2C35F627C6) the use of a simple switch as a binary input 2, and paragraph 8-digit binary display 16 results. Platform: |
Size: 7168 |
Author:王媛媛 |
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Description: TPLSLED7Seg is a Delphi Visual Component representing a Seven
Segment LED digit, used in digital clocks, counters and a host
of other electronic equipment. Platform: |
Size: 174080 |
Author:anung |
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Description: 用vhdl语言编译一个码制转换
四位二进制->BCD码，然后将BCD码->七段显示器码。
（1）当输入为0~9的数时，其十位数为0，个位数=输入。
当输入为10~15的数时，其十位数为1，个位数=输入-10。
（2）然后将十位和个位的BCD码转换为七段显示码
-Vhdl language used to compile a binary code system conversion of four-> BCD code, then BCD code-> seven-segment display code. (1) When the input is a number from 0 to 9, its ten digits 0 digits = input. When the input is 10 to 15 the number, the tens digit is 1, digits = input-10. (2) and then ten and a bit BCD code is converted to seven segment display code Platform: |
Size: 326656 |
Author:宋子皓 |
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Description: This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be easily ported to other fpga s. Platform: |
Size: 8192 |
Author:hatsjoe |
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Description: 基于51单片机的秒表程序，包含一个中断，单片机入门的最好材料，三个按键，两位七段数码管组成，简单易懂。-51 MCU based stopwatch program, includes an interrupt, the best material SCM entry, three keys, two digit seven segment digital tube, easy to understand.
Platform: |
Size: 27648 |
Author:李生 |
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Description: 本次设计主要基于FPGA器件完成了一个IC电话计费器的设计，其能够显示用户IC的卡值余额，并能够根据用户当前的话务种类和通话时间进行扣费，并将用户的实时余额和通话时间通过4位LED七段显示器显示出来。整个设计过程采用自顶向下的分块设计方法，即将整个电话计费系统分为电话计费、计时模块和显示模块两大模块，其各模块的实现是基于QuartusⅡ9.2平台使用DE0硬件描述语言编程实现的。-This design is mainly based FPGA devices completed a telephone billing IC design, which can show the user the value of the IC card balance, and according to the user' s current traffic types and talk time for deductions, and the user' s real-time balance and talk time via 4-digit LED seven segment display display. Throughout the design process using a top-down design approach block, the entire telephone billing system will be divided into telephone billing, timekeeping module and display module into two modules, each module of its implementation is based on Quartus Ⅱ 9.2 platform using hardware description DE0 language programming. Platform: |
Size: 223232 |
Author:王渊 |
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Description: VHDL语言设计老虎机的方案：
1、对DE2内部时钟实现分频，产生50hz的计数频率CLK；
2、用CLK作为计数时钟，分别实现三个计数器0~11,0~13,0~17，并将其计数结果中的个位数分别用三个七段数码管显示HEX1、HEX2、HEX3；
3、用CLK对DE2上的key1按键实现“定时方式去毛刺”输出K_Press信号，参见教材262；
4、利用K_Press信号的上升沿信号，实现Enable信号的翻转；Enable作为三个计数器的使能端，决定计数器的停止或者开始运行；
5、停止计数时，比较三个计数器的输出数字的相同个数N，并用七段数码管HEX4输出。N的结果分别为0、2、3；其中“0”表示三个数字中没有任何两个数字相同
-VHDL language program designed slot machine: 1, DE2 internal clock divider to generate 50hz frequency count of CLK 2, with the CLK as the count clock, respectively, to achieve three counters 0 ~ 11,0 ~ 13,0 ~ 17, and to count the results were used in the three-digit seven-segment LED display HEX1, HEX2, HEX3 3, with the CLK button for key1 DE2 on the realization of " regular way deburring" K_Press output signal, see textbooks 262 4 , the rising edge of the signal using the signal K_Press, flipping the Enable signal Enable counter as an enable terminal of three decision to stop or start operation of the counter 5, the counting is stopped, comparing the same number of three-digit counter output N, and pipe HEX4 segment digital output. Results N 0,2,3 respectively where " 0" indicates that no two of the three figures the same number Platform: |
Size: 2951168 |
Author:武生 |
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Search - 2 digit seven segment