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Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
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Size: 845501 |
Author: citybus |
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Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.
Platform: |
Size: 899078 |
Author: lee |
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Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
Platform: |
Size: 844800 |
Author: citybus |
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Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的PCI位码文件及配置程序。-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of the PCI code files and configuration procedures.
Platform: |
Size: 416768 |
Author: zhao onely |
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Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.-PCI Design Guide The Xilinx LogiCORE PCI interface is a fully verified, pre-implementedPCI Bus interface. This interface is available in 32-bit and 64-bit versions, with support for multiple Xilinx FPGA device families. Itis designed to support both Verilog-HDL and VHDL. The designexamples in this book are provided in Verilog.
Platform: |
Size: 899072 |
Author: lee |
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Description: pci 32位的core的实现源代码，我晕阿，实在是不好怎么说阿-pci 32-bit core of the realization of the source code, I fainted Ah, how to say it is not Arab. . . .
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Size: 30720 |
Author: adfdf |
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Description: PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL!
Author is Ovidiu Lupas!
MASTER model
generates PCI compliant signals
checks Target signal compliance with PCI
checks data received from Target for correctness
generates assertion reports if Target signals are not PCI compliant
TARGET model
generates PCI compliant signals
checks Master signal compliance with PCI
checks data received from Master for correctness
generates assertion reports if Master signals are not PCI compliant
Description
The models are boardlevel simulation models and are useful in the testing phase
of
the PCI cores design. The models are 32 bit, 33 MHz PCI compliant but are easy
upgradable to 64 bit, 66 MHz. The models are free you can redistribute them
and/or modify them under the terms of the GNU General Public License as
published by the Free Software Foundation either version 2 of the License, or
(at your option) any later version.
The models are distributed in the hope that they will be useful, but WITH
Platform: |
Size: 6144 |
Author: kity |
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Description: 32位33Mhz PCI接口程序设计参考，芯片是Lattice
-32-bit 33Mhz PCI interface programming reference chip is Lattice
Platform: |
Size: 8192 |
Author: chenguochun |
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