Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed. Platform: |
Size: 179551 |
Author:李中伟 |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed. Platform: |
Size: 179200 |
Author:李中伟 |
Hits:
Description: 用VHDL写的一个32位并行乘法器的源代码，已经过验证，可以直接使用-Use VHDL to write a 32-bit parallel multiplier source code, has already been verified, you can directly use Platform: |
Size: 1024 |
Author:zh |
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Description: The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one.-The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one. Platform: |
Size: 172032 |
Author:farbosein |
Hits:
Search - 32 bit multiplier in vhdl