Search - 32bit Verilog

[VHDL-FPGA-Verilog] miniMIPS

Description: 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS- I structure of the processor, 32bit, von Neumann structure
Platform: | Size: 222208 | Author: tsm998 | Hits:

[VHDL-FPGA-Verilog] Lab20

Description: the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication.
Platform: | Size: 56320 | Author: 王琪 | Hits:

[VHDL-FPGA-Verilog] alu_32_bit

Description: verilog 32-bit ALU-verilog 32-bit ALU
Platform: | Size: 2048 | Author: qwasqwas | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

[VHDL-FPGA-Verilog] 32_16div

Description: 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
Platform: | Size: 1024 | Author: 郭勇谅 | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[VHDL-FPGA-Verilog] alu32bit

Description: verilog hdl alu module it is 32bit alu and 1bit alu
Platform: | Size: 368640 | Author: park | Hits:

[VHDL-FPGA-Verilog] pci32lite_oc

Description: PCI 32bit Slave Verilog 代码-PCI 32bit Slave Verilog code
Platform: | Size: 18432 | Author: chen | Hits:

[VHDL-FPGA-Verilog] Adder_Kogge_Stone_32bit_With_Test_Bench

Description: verilog source code and test bench of Adder Kogge Stone 32-Bit
Platform: | Size: 528384 | Author: abanuaji | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: verilog implementation of the 32bit multiplier
Platform: | Size: 1024 | Author: ramtin | Hits:

Description: 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. And through the Lookahead algorithm improve the efficiency, significant savings in computing time. ASC process can be simulated by its internal circuit. Code, process documents, readme in the folder
Platform: | Size: 13528064 | Author: 杨岩 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
Platform: | Size: 19456 | Author: qc | Hits:

[VHDL-FPGA-Verilog] campur

Description: total added value for 6 data in 32bit floating point for verilog code
Platform: | Size: 3072 | Author: hafiez | Hits:

[VHDL-FPGA-Verilog] 6data-power2verilog

Description: verilog code (power two) for 6 data entry in 32bit floating point
Platform: | Size: 1024 | Author: hafiez | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

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