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[
VHDL-FPGA-Verilog
]
AdderSubtractor
Description:
4-Bit Adder Subtractor Verilog Code. (Complete project)
Platform:
|
Size:
306176
|
Author:
gunkaragoz
|
Hits:
[
VHDL-FPGA-Verilog
]
add_ded_module
Description:
使用Verilog语言编写的4位加减法器,经验证能在FPGA开发板上实现。-Verilog4 bit adder-subtractor.
Platform:
|
Size:
345088
|
Author:
李泽骏
|
Hits:
[
VHDL-FPGA-Verilog
]
verilog-source-codes
Description:
the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
Platform:
|
Size:
2048
|
Author:
apparao
|
Hits:
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