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[Embeded-SCM Develop] 429_enc_dec

Description: Quartus开发环境下开发的Arinc 429总线收发器工程，由于产权问题，提供的程序有删减，标号未尽规范。-Quartus development environment developed under the Arinc 429 bus transceiver works, because the issue of property rights, provided procedures are deleted, not standardized labeling.
Platform: | Size: 679936 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] series_port

Description: 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
Platform: | Size: 5120 | Author: 小刘 | Hits:

[VHDL-FPGA-Verilog] rt_32bit

Description: 通过Verilog实现的基于FPGA实现429总线格式转换接收程序-FPGA code for receive 429 message
Platform: | Size: 38435840 | Author: 里 | Hits:

[VHDL-FPGA-Verilog] 429NEW-03-15

Description: 429总线通过FPGA直接实现发送程序,通过Verilog实现-send 429 message by Verilog and FPGA
Platform: | Size: 22150144 | Author: 里 | Hits:

[Other] arinc429_receiver

Description: Simple Arinc-429 receiver channel description on Verilog HDL with parameterized DATA and LABEL FIFOs.
Platform: | Size: 6144 | Author: scnn86 | Hits:

[VHDL-FPGA-Verilog] arinc429_transmitter

Description: Simple Arinc-429 transmitter channel description on Verilog HDL with parameterized DATA FIFO.
Platform: | Size: 4096 | Author: scnn86 | Hits:

[VHDL-FPGA-Verilog] ARINC429航空总线协议标准

Description: 429总线，协议及相关介绍，机载航电设备通讯总线(FPGA implementation ARINC429 protocol using verilog HDL to do a complete ARINC429 communication transceiver protocol,)
Platform: | Size: 354304 | Author: shukuang | Hits:

[Other] hi3585

Description: verilog code for hi3585 SPI control code .HI3585 is a arinc 429 bus protocol.
Platform: | Size: 6144 | Author: TBlue | Hits:

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