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[Other resource] SRAM_16Bit_512K

Description: Verilog 编写的IP核，512K的16位SRAM
Platform: | Size: 11531 | Author: zhyy | Hits:

[Other Embeded program] SRAM_16Bit_512K

Description: DE2板子附带的SRAM IPCORE 有兴趣的朋友可以下载-DE2 board attached SRAM IPCORE friends who are interested can download
Platform: | Size: 11264 | Author: huang | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: | Size: 11264 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: 一个sram的源码程序，它是256kbx16bit的sram-An SRAM of the source program, it is the SRAM 256kbx16bit
Platform: | Size: 11264 | Author: chenyizhong | Hits:

[Other] LY625128[1]

Description: LY625128 静态存储器，512K容量，大容量静态存储器-LY625128 SRAM, 512K capacity, large-capacity SRAM
Platform: | Size: 329728 | Author: dingchaohai | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: SRAM 16B 512K容量的控制器-SRAM 16B 512K capacity control
Platform: | Size: 11264 | Author: 徐伟伟 | Hits:

[Other Embeded program] External_interface_to_512K_SRAM

Description: This file provides an example of connecting a 512k SRAM as an external memory to the Renesas M16C microcontroller.
Platform: | Size: 7593984 | Author: Todd TERRY | Hits:

[Other] sram_if

Description: 实现跟sram芯片的接口。调试时使用的芯片是：IS61WV51216BLL-10T，容量512K words，总线16位。 模块工作时钟为100MHz.-Achieved with sram chip interface. The chip is used for debugging: IS61WV51216BLL-10T, Capacity 512K words, the bus 16. Module clock is 100MHz.
Platform: | Size: 2048 | Author: liujiakui | Hits:

[Other] 外部SRAM实验 512K

Description: 芯片stm32f103 IS62WV25616 测试(Chip STM32F103 IS62WV25616 test)
Platform: | Size: 3440640 | Author: 1038469668 | Hits:

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