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[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
Platform: | Size: 1012462 | Author: 李华 | Hits:

[USB develop] cy7c68013

Description: usb 2.0 cy7c68013 pdf file
Platform: | Size: 516096 | Author: flight_bai | Hits:

[USB develop] cmos_fifo_usb

Description: cmos数据到fifo再到usb的fifo部分程序(68013a)-cmos data to fifo the fifo to the usb part of the procedures (68013a)
Platform: | Size: 158720 | Author: | Hits:

[MiddleWare] fpga_fifo_0122_02

Description: 可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序-To amend the agreement in the inside. Mainly cmos-fpga usb (68013a), except part of the procedure 68013a
Platform: | Size: 2322432 | Author: | Hits:

[Embeded-SCM Develop] 999

Description: CY7C68013开发板原理图 C Y7C68013开发板原理图 CY7C68013开发板原理图-CY7C68013 development board schematics C Y7C68013 development board development board schematics CY7C68013 Schematic
Platform: | Size: 74752 | Author: alin | Hits:

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
Platform: | Size: 4731904 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] USB2_0

Description: USB2_0控制器CY7C68013与FPGA接口的VerilogHDL实现.rar-CY7C68013 and FPGA controller USB2_0 interface VerilogHDL achieve. Rar
Platform: | Size: 365568 | Author: fiann | Hits:

[Embeded-SCM Develop] Flash_FPAG_JTAG

Description: FPGA或者CPLD通过JTAG接口对FLASH进行读写的资料。非常有用-Programming Flash Memory from FPAGs and CPLDs Using the JTAG Port. Very useful
Platform: | Size: 305152 | Author: superstar | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验 结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[VHDL-FPGA-Verilog] CY7C68013

Description: USB2.0的Verilog实现，含有完整的FPGA代码-Use Verilog to implement the USB2.0 protcol
Platform: | Size: 600064 | Author: XCP | Hits:

[VHDL-FPGA-Verilog] SLAVE_FIFO_16BITS

Description: 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
Platform: | Size: 1625088 | Author: xinsheng | Hits:

[VHDL-FPGA-Verilog] usb_wr_Verilog

Description: fpga ubs通讯模块 verlog语言 使用EZ-USB FX2-USB interface. use EZ-USB FX2 carry out PC communication with FPGA by USB.
Platform: | Size: 31744 | Author: shenjianfei | Hits:

[VHDL-FPGA-Verilog] 68013

Description: 使用68013的测试程序，包含68013固件程序-use of cy7c68013,data transfer from usb to pc.
Platform: | Size: 4718592 | Author: 杨小兽 | Hits:

[VHDL-FPGA-Verilog] fifo_FPGA

Description: 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)
Platform: | Size: 887808 | Author: 郑韬 | Hits:

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