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Description: 组成原理实验所用，关于组成原理的不少期间会有很大用途
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Size: 1902451 |
Author: 朱亭亭 |
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Description: 组成原理实验所用，关于组成原理的不少期间会有很大用途-Principle components used in the experiment, on the composition of the principle that there might be a great many uses
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Size: 1902592 |
Author: 朱亭亭 |
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Description: 利用SST89E516实现24LED跑灯，其中运用的，74LS161三片，原理图不知道弄那去了。找到的时候再传上来。-24LED use to achieve SST89E516 running lights, which use, 74LS161 3, schematic diagram do not know get it going. Send up to find the time.
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Size: 16384 |
Author: 刘东 |
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Description: 给予quartus II 软件
verilog 描述的 74ls161 包含仿真波形 -verilog 74ls161 quartus II
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Size: 54272 |
Author: xu |
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Description: 74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl
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Size: 1209344 |
Author: 曹旭 |
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Description: 74ls283 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl
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Size: 378880 |
Author: 曹旭 |
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Description: 用74ls161编的数字电路时钟图.方便刚接触单片机的人学习-Series of digital circuits with 74ls161 clock map
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Size: 241664 |
Author: 董永 |
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Description: 使用51单片机，以及74LS161芯片，对脉冲进行计数，提供详细的相关芯片资料，仿真文件，可直接观看运行效果。 -51 single use, and 74LS161 chips, the pulse count, providing detailed information related to the chip, the simulation files can be run directly watch the effect.
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Size: 1348608 |
Author: |
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Description: 采用8位右移寄存器74ls164实现8个彩灯的向右移动，从它的右移输入端输入四种码，来实现它的四种花样，根据四种花样确定四种码，可通过模16计数器74ls161的输出端接与门74ls08和非门74ls04产生。-8-bit right shift register 74ls164 move to the right of the eight lanterns, it s shifted to the right input of the input four kinds of code, to achieve its four pattern, four kinds of tricks to identify four yards, through the mold 16the counter 74ls161 output termination with the door 74ls08 and by non-door 74ls04 generated.
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Size: 1024 |
Author: mary |
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Description: 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and computing method for the preparation of the 290 counter: Another compilation Act LS290 8 line decoder can end line without eight JK flip-flop election with a number of selector: full adder CASE statement:
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Size: 7168 |
Author: Lynn |
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Description: 数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能-Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function
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Size: 501760 |
Author: 苏婧 |
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Description: 用Maxplus2制作的实现74LS161数字芯片功能，入门级工程。-Maxplus2 made with digital chips to achieve 74LS161 function, entry-level engineering.
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Size: 23552 |
Author: 杰克 |
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Description: 用74ls161实现60进制计数功能，异步清零法(74161 to achieve 60 hexadecimal)
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Size: 106496 |
Author: fpgaaaaaaa
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Description: 用VHDL语言实现74LS161的功能，以及用74LS161实现模19计数器的功能(Using VHDL language to achieve the function of 74LS161, as well as using 74LS161 to achieve modulo 19 counter function)
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Size: 262144 |
Author: 山丘叶
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Description: 基于底层器件为161的一个计数器控制两个模值的计数器(a counter control two mode value)
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Size: 6144 |
Author: nywy |
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