Description:
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later Platform: |
Size: 73116 |
Author:聂样 |
Hits:
Description:
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later Platform: |
Size: 72704 |
Author:聂样 |
Hits:
Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC
cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of
codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device
for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is
implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC
code． Platform: |
Size: 165888 |
Author:秦小星 |
Hits:
Search - 8 10 encoding vhdl