Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram Platform: |
Size: 4933632 |
Author:李星 |
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Description: 为提高8051系列单片机I2C总线的工作效率，提高整机工作性能，根据I2C总线协议设计了8051单片机的I2C接口电路。-To enhance the 8051 Series Single-chip I2C bus efficiency, improve machine performance, in accordance with I2C bus protocol designed 8051 the I2C interface circuit. Platform: |
Size: 1425408 |
Author:laomo |
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Description: 用VHDL写的一个SPI接口程，调试通过，曾多次用项目中，感非常好用，与大家分享。-Use VHDL to write an SPI interface process, debugging is passed, with the project on several occasions, the flu is very useful to share with you. Platform: |
Size: 52224 |
Author:刘林 |
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Description: This file provides an 8051 external data memory bus interface
for CoolRunner CPLDs. This file contains the state machine to
interface on the 8051 bus as well as the address registers, the address
decode logic, and example control registers, status registers, data input
registers, and data output registers. Interrupt logic is also included.
Note that this code should be modified to meet the requirements of the
system.
-This file provides an 8051 external data memory bus interface
for CoolRunner CPLDs. This file contains the state machine to
interface on the 8051 bus as well as the address registers, the address
decode logic, and example control registers, status registers, data input
registers, and data output registers. Interrupt logic is also included.
Note that this code should be modified to meet the requirements of the
system.
Platform: |
Size: 4096 |
Author:alex |
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Description: VHDL源码 8051+IP内核 在xilinx环境仿真运行 不带接口的逻辑部分代码-VHDL source code 8051+ IP cores in the xilinx environment simulation to run without a logical part of the code interface Platform: |
Size: 98304 |
Author:王力 |
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Description: This contains the main-level VHDL files required for an example complete, ready-to-use,
FPGA/ASIC 8051 microcontroller. The corresponding main schematic can be found in the
Schematics folder, and a technical description of the e8051 core interface in the “Data
sheets/e8051 User Guide” file-This contains the main-level VHDL files required for an example complete, ready-to-use,
FPGA/ASIC 8051 microcontroller. The corresponding main schematic can be found in the
Schematics folder, and a technical description of the e8051 core interface in the “Data
sheets/e8051 User Guide” file Platform: |
Size: 504832 |
Author:h_j_tel |
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Description: In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord.
Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication. In this lab, we ll try to build a serial link between 8051 and PC using RS232.
Platform: |
Size: 374784 |
Author:mezzich |
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