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[VHDL-FPGA-Veriloga8254

Description: 自己编写的8254计数器/计时器,实现了所有的6种模式,和大家一起分享。-I have written 8254 counter/timer, realize all the six kinds of patterns, and the U.S. share.
Platform: | Size: 4881408 | Author: 高超 | Hits:

[assembly languagedzz

Description: 设计一个定时显示装置,用实验仪左侧的六个LED数码管显示时间,时间显示格式为24小时制。分秒值为59分55秒时开始报时,每秒钟蜂鸣器鸣叫一声,到整点报时停止。 74系列模块;8254模块;8259模块;8255模块。 在PD32实验模块中验证正确 8254每25ms刷新依次 Q_0、Q_1、Q_2、Q_3分别与Q0、Q1、Q2、Q3相连 P_0、P_1、P_2分别与P0、P1、P2相连 74: CS1接340H,CS2接360H GATE0接+5V,CLOCK0接1.5MHZ,OUT0接IR0,GATE1接8255第四片B0,CLOCK1接93KHZ,OUT1接蜂鸣器,CS接300H,A0接地址线A2,A1接地址线A3 8259CS1接3A0H,INT1接INTR,INT-A接INTA,SP/1接+5V 8255CS4接CS-4-Shows the design of a timing device, the experimental instrument with the left side of the six LED digital time display, time display format for the 24-hour clock. Accurate value of 59 minutes and 55 seconds at the beginning of time, calls out every second buzzer to stop the whole point of time. 74 series module 8254 module 8259 module 8255 module. PD32 experimental module in the right to verify each and every 25ms refresh 8254 followed Q_0, Q_1, Q_2, Q_3 with Q0, Q1, Q2, Q3 connected to P_0, P_1, P_2, respectively, and P0, P1, P2 connected 74: CS1 access 340H, CS2 Access 360H GATE0 then+5 V, CLOCK0 then 1.5MHZ, OUT0 then IR0, GATE1 the fourth film 8255 then B0, CLOCK1 then 93KHZ, OUT1 access buzzer, CS next 300H, A0 then address line A2, A1 then take the address line A3 8259CS1 3A0H, INT1 then INTR, INT-A Access INTA, SP/1 then+5 V 8255CS4 then CS-4
Platform: | Size: 2048 | Author: 康凯 | Hits:

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