Search - 8B 10B

[Other resource] 8b_10b

Description: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 73116 | Author: 聂样 | Hits:

[Develop Tools] qianzhaoyitaiwang

Description: pdf格式电子书第一部分千兆以太网基础第1章千兆网之前的以太网第2章从共享介质到专用介质第3章从共享式LAN到专用LAN 第4章全双工以太网第5章帧格式第6章以太网流量控制第7章以太网的介质无关性第8章自动配置第二部分千兆以太网技术第9章千兆以太网体系结构及概述第10章千兆以太网介质访问控制第11章千兆以太网集线器第12章千兆以太网的物理层第13章千兆以太网标准简介第三部分千兆以太网应用第14章应用环境第15章性能问题第16章其他的技术方案附录 8B/10B代码表-pdf format for the first part of e-books based Gigabit Ethernet Chapter 1 Gigabit Ethernet network before the Chapter 2 from the shared medium dedicated to the medium Chapter 3 from the shared LAN to LAN dedicated full-duplex Chapter 4 Chapter 5 Ethernet frame format Chapter 6 Ethernet flow control Chapter 7 Ethernet Media Independence Chapter 8 automatic configuration part of the second Gigabit Ethernet technology Chapter 9 Gigabit Ethernet Architecture and outlined Chapter 10 Gigabit Ethernet MAC Chapter 11 Gigabit Ethernet hub Chapter 12 Gigabit Ethernet physical layer Chapter 13 Gigabit Ethernet standard profiles the third part of Gigabit Ethernet Application of Chapter 14 application environment Chapter 15 Performance Chapter 16 other technical programs 8B/10B code Appendix Table
Platform: | Size: 12334494 | Author: 许先生 | Hits:

[Books] qianzhaoyitaiwang

Description: pdf格式电子书第一部分千兆以太网基础第1章千兆网之前的以太网第2章从共享介质到专用介质第3章从共享式LAN到专用LAN 第4章全双工以太网第5章帧格式第6章以太网流量控制第7章以太网的介质无关性第8章自动配置第二部分千兆以太网技术第9章千兆以太网体系结构及概述第10章千兆以太网介质访问控制第11章千兆以太网集线器第12章千兆以太网的物理层第13章千兆以太网标准简介第三部分千兆以太网应用第14章应用环境第15章性能问题第16章其他的技术方案附录 8B/10B代码表-pdf format for the first part of e-books based Gigabit Ethernet Chapter 1 Gigabit Ethernet network before the Chapter 2 from the shared medium dedicated to the medium Chapter 3 from the shared LAN to LAN dedicated full-duplex Chapter 4 Chapter 5 Ethernet frame format Chapter 6 Ethernet flow control Chapter 7 Ethernet Media Independence Chapter 8 automatic configuration part of the second Gigabit Ethernet technology Chapter 9 Gigabit Ethernet Architecture and outlined Chapter 10 Gigabit Ethernet MAC Chapter 11 Gigabit Ethernet hub Chapter 12 Gigabit Ethernet physical layer Chapter 13 Gigabit Ethernet standard profiles the third part of Gigabit Ethernet Application of Chapter 14 application environment Chapter 15 Performance Chapter 16 other technical programs 8B/10B code Appendix Table
Platform: | Size: 12334080 | Author: 许先生 | Hits:

[VHDL-FPGA-Verilog] Giga8b10b v10

Description: 可编程器件厂商Altera出品的8b10b编码器，用在现在通用的PCI－Express接口中，包含完全解密的源程序。-Altera programmable device manufacturers buy 8b10b encoder, now with the generic PCI-Express interface, including full decryption of the source.
Platform: | Size: 18432 | Author: 宋云成 | Hits:

[VHDL-FPGA-Verilog] 8b10b_Decoder

Description: 应用VHDL设计的8b10b解码器源文件，实现高速的串行数据传输。-application VHDL design 8b10b decoder source, the realization of high-speed serial data transmission.
Platform: | Size: 18432 | Author: | Hits:

[VHDL-FPGA-Verilog] 8b_10b

Description: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 72704 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilog] 8b10b_encdec

Description: VHDL写的8B10B编码解码器的实现，在Xilinx平台通过验证。-Written in VHDL coding 8B10B decoder realize, in the Xilinx platform validated.
Platform: | Size: 70656 | Author: 张开文 | Hits:

[VHDL-FPGA-Verilog] 8b10b_encdec

Description: 8b10b转换编码、解码verilog源代码-8b10b transcoding, decoding verilog source code
Platform: | Size: 70656 | Author: wx | Hits:

[VHDL-FPGA-Verilog] 8B-10B

Description: 一种新的8B-10B编解码硬件设计方法，希望对您的工作有所帮助。-A new codec 8B-10B hardware design, and I hope to be helpful to your work.
Platform: | Size: 94208 | Author: 王坤 | Hits:

[SCM] uart

Description: 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a start bit, 8 data bits, one stop bit.It has been verified in the development-board of actel Fusion Series , and is highly versatile.The programming language used in this module is verilog.
Platform: | Size: 2048 | Author: 何斌 | Hits:

[Software Engineering] 8b10b_encdec

Description: 8b/10b encoder/decoder vhdl source-8b/10b encoder/decoder vhdl source
Platform: | Size: 141312 | Author: ZES | Hits:

[Other] SerialATA-Revision-2-6-Gold

Description: Serial Advanced Technology Attachment (SATA) is a serial link replacement of Parallel ATA (PATA), both standards for communication with mass storage devices. This high-speed serial link is a differential layer that utilizes Gigabit technology and 8b/10b encoding. Some of the features of SATA compared to PATA are increased transfer speed, hot-plug capability, and Native Command Queuing (NCQ). The link supports full duplex but the protocol only permits frames in one direction at a time. The other non-data direction is used for flow control of the data stream. Figure 2.1. The layers of the SATA protocol SATA’s architecture consists of four layers (see Figure 2.1), Application, Transport, Link, and Physical. The Application layer is responsible for overall ATA commands 7
Platform: | Size: 6769664 | Author: hamza | Hits:

[Other] 8b10b_table

Description: 8b 10b encrypting, all combinations
Platform: | Size: 25600 | Author: Yaguar | Hits:

[Other] 8b10b

Description: 8b10b转换编码的verilog描述，非常好-8b/10b trans
Platform: | Size: 8192 | Author: 吴增海 | Hits:

[ELanguage] 16b20b_Decoder

Description: VHDL实现的16B/20B解码器。包含两个8B/10B解码器。采用级联方式实现-VHDL implementation 16B/20B decoder. Contains two 8B/10B decoder. Be achieved by cascading
Platform: | Size: 31744 | Author: Kevin | Hits:

[ELanguage] 16b20b_Encoder

Description: VHDL实现的16B/20B编码器。由两个8B/10B编码器组成。级联实现。-VHDL implementation 16B/20B encoder. Composed by two 8B/10B encoder. Cascade realization.
Platform: | Size: 78848 | Author: kvein | Hits:

[VHDL-FPGA-Verilog] MEdia_control_i2c

Description: 将来自MAC的GMII8B码进行8B/10B编码。FPGA输出10路10B码的数据，如有必要，可配置外挂SDRAM，FPGA还得实现SDRAM控制器，-Will come from the MAC' s GMII8B codes 8B/10B encoding. FPGA output 10 Road 10B code data, if necessary, can be configured to plug SDRAM, FPGA have to realize SDRAM controller
Platform: | Size: 35840 | Author: 刘强为 | Hits:

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[Other resource] 8b_10b

[Develop Tools] qianzhaoyitaiwang

[Books] qianzhaoyitaiwang

[VHDL-FPGA-Verilog] Giga8b10b v10

[VHDL-FPGA-Verilog] 8b10b_Decoder

[VHDL-FPGA-Verilog] 8b_10b

[VHDL-FPGA-Verilog] 8b10b_encdec

[VHDL-FPGA-Verilog] 8b10b_encdec

[VHDL-FPGA-Verilog] 8B-10B

[SCM] uart

[Software Engineering] 8b10b_encdec

[Other] SerialATA-Revision-2-6-Gold

[Other] 8b10b_table

[Other] 8b10b

[ELanguage] 16b20b_Decoder

[ELanguage] 16b20b_Encoder

[VHDL-FPGA-Verilog] MEdia_control_i2c

[VHDL-FPGA-Verilog] ENCODE_8B_10B

[VHDL-FPGA-Verilog] 8b10b_encdec_latest.tar

[VHDL-FPGA-Verilog] 8b10b-master

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