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Description:
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later
Platform: |
Size: 73116 |
Author: 聂样 |
Hits:
Description: 可编程器件厂商Altera出品的8b10b编码器，用在现在通用的PCI－Express接口中，包含完全解密的源程序。-Altera programmable device manufacturers buy 8b10b encoder, now with the generic PCI-Express interface, including full decryption of the source.
Platform: |
Size: 18432 |
Author: 宋云成 |
Hits:
Description:
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: |
Size: 72704 |
Author: 聂样 |
Hits:
Description: 8b/10b encoder/decoder vhdl source-8b/10b encoder/decoder vhdl source
Platform: |
Size: 141312 |
Author: ZES |
Hits:
Description: VHDL实现的16B/20B编码器。由两个8B/10B编码器组成。级联实现。-VHDL implementation 16B/20B encoder. Composed by two 8B/10B encoder. Cascade realization.
Platform: |
Size: 78848 |
Author: kvein |
Hits:
Description: Encoder to create TLP s for data trasmission.
Platform: |
Size: 1024 |
Author: Nikhil |
Hits:
Description: vhdl开发，8b—10b 编解码器设计Encoder: 8bb/10b Encoder (file: 8b10b
-vhdl development, 8b-10b codec design Encoder: 8bb/10b Encoder (file: 8b10b
Platform: |
Size: 72704 |
Author: nu |
Hits:
Description: this a vhdl code to simulate 8b/10b encoder and decoder with a test bench-this is a vhdl code to simulate 8b/10b encoder and decoder with a test bench
Platform: |
Size: 135168 |
Author: zaki-sammani |
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