Search - AC vhdl

[VHDL-FPGA-Verilog] v1

Description: 交流电压表相应的VHDL代码，帮助大家打开一下思路-AC voltage Table corresponding VHDL code, help you open some ideas
Platform: | Size: 787456 | Author: 白杨 | Hits:

[Other] ac97controller

Description: ac`97 controller verilog codes-ac `97 controller verilog codes
Platform: | Size: 16384 | Author: fxs | Hits:

[VHDL-FPGA-Verilog] dianyabiao

Description: 基于ISD4004的语音报值交直流电压表的设计：本文介绍了基于语音芯片ISD4004的语音报值交直流电压表的设计。电路由数据采集部分，A/D转换部分，键盘与显示部分，单片机控制部分，语音报值部分和扩展功能部分组成。电路使用了并行与串行总线相结合的方式，使设计与编程灵活简便。创意新颖有趣，富于人性化，避免了频繁观察仪器显示之苦，对减轻工程技术人员的工作量和提高工作效率现实意义。-ISD4004 voice-based value of AC and DC voltage at the design table: In this paper, based on the voice chip ISD4004 voice at the value of AC-DC voltage meter design. Part by the data acquisition circuit, A/D conversion of part of the keyboard and display, single-chip control of the reported value of part of speech and expand the functional parts. The use of a parallel circuit with a combination of serial bus, so as to enable convenient and flexible design and programming. Innovative ideas interesting and full of humanity, to avoid the frequent observation shows that the hardship of equipment, engineering and technical personnel to reduce workload and improve the efficiency of practical significance.
Platform: | Size: 475136 | Author: song | Hits:

[VHDL-FPGA-Verilog] audio_codec

Description: i2s协议时飞利浦公司专门为开发音频而开发的协议，这是它的VHDL代码，希望有帮助-i2s agreement, Philips developed specifically for the development of the audio protocol, which is its VHDL code, and want to help
Platform: | Size: 1742848 | Author: 王涛 | Hits:

[Other] E1-FramerDeframer

Description: E1 Framer/Deframer,E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note:This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department / Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi-E1 Framer/Deframer, E1 framer Deframer core implements CCITT (ITU) recommedations G.704, G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note: This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department/Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi
Platform: | Size: 139264 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 实验箱的蜂鸣器是交流蜂鸣器，在BZSP输入一定频率的脉冲时，蜂鸣器蜂鸣，改变输入频率可以改变蜂鸣器的响声。因此可以利用一个PWM来控制BZSP，通过改变PWM的频率来得到不同的声响，以此来播放音乐。-Experiment Box AC buzzer buzzer is in BZSP certain frequency pulse input, the buzzer beeps to change the input frequency can change the sound of the buzzer. So you can use a PWM to control BZSP, by changing the PWM frequency to get different sounds in order to play music.
Platform: | Size: 22528 | Author: 王记存 | Hits:

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[VHDL-FPGA-Verilog] v1

[Other] ac97controller

[VHDL-FPGA-Verilog] dianyabiao

[VHDL-FPGA-Verilog] audio_codec

[Other] E1-FramerDeframer

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] INVERTER

[Other] ac-volt-generator

[Compress-Decompress algrithms] ac

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