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[SCM] adc

Description: 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。-The preparation of Verilog code box on the use of experimental A/D chip to complete analog-digital conversion. Input voltage provided by the experimental box, and its amplitude in the 0 ~ 5V between changes in control by potentiometer. Output signal shows that the value of analog voltage input from a digital display for two BCD code of the form.
Platform: | Size: 22528 | Author: Ericwhu | Hits:

[VHDL-FPGA-Verilog] xapp355

Description: Serial ADC Interface write in VHDL based on xilinx cpld
Platform: | Size: 33792 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] ADC

Description: 用verilog编程实现的基于FPGA的AD数据采集程序-Verilog Programming with FPGA-based data collection procedures AD
Platform: | Size: 499712 | Author: 张西贝 | Hits:

[VHDL-FPGA-Verilog] adc_verilog

Description: adc verilog 用verilog编写的sigma-delta adc例子 应用在计量类adc产品-adc verilog Verilog prepared using sigma-delta adc examples used in the measurement adc Product category
Platform: | Size: 3072 | Author: 张鸿 | Hits:

[VHDL-FPGA-Verilog] ADC_INTERFACE

Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
Platform: | Size: 6144 | Author: yasir ateeq | Hits:

[Other] verilog-A_library

Description: Complete Verilog-A library for analog blocks, like ADC, DAC, amplifiers
Platform: | Size: 80896 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] adc2

Description: ADC control in VHDL language. Spartan 3E starter pack ISE 10.1
Platform: | Size: 203776 | Author: khoosram | Hits:

[VHDL-FPGA-Verilog] 16bitADC

Description: verilog实现的16位模数转换器参考源代码-verilog to achieve 16-bit ADC reference source code
Platform: | Size: 1024 | Author: 龚俊杰 | Hits:

[Other] part1_2.tar

Description: this a 10bit 80MSample/sec SAR ADC with offset cancellation capability (implemented in verilog)-this is a 10bit 80MSample/sec SAR ADC with offset cancellation capability (implemented in verilog)
Platform: | Size: 288768 | Author: meteora | Hits:

[VHDL-FPGA-Verilog] adc

Description: 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
Platform: | Size: 3072 | Author: 钟雪美 | Hits:

[VHDL-FPGA-Verilog] ADC-

Description: it is the document & source code in verilog of adc using sparten 3e fpga kit
Platform: | Size: 721920 | Author: kamlesh | Hits:

[Software Engineering] ADC_16bit.v

Description: 一个verilog编写的16位ADC程序。该程序方便了DAC的设计人员对DAC提供输入信号，以此可以获得理想的DAC所需信号-Verilog to write a 16-bit ADC program. The program facilitates the DAC' s designers to provide input signals to the DAC, in order to be able to get a good DAC desired signal
Platform: | Size: 1024 | Author: 徐振涛 | Hits:

[Other Embeded program] adc

Description: VERILOG编程，利用状态机实现对TLC549的采样控制，实验时可调节电位器RW1（在开发板底板左下角），改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。 -Implementation of sampling control of TLC549 using state machine, adjustable potentiometer RW1 experiment (in the development board bottom left corner), change the ADC The analog input values, data acquisition and read in the digital tube display.
Platform: | Size: 1024 | Author: suzhangzhan | Hits:

[VHDL-FPGA-Verilog] tugedafinal

Description: 使用Verilog HDL语言写的关于实现对ADC、MDC控制的程序，个人使用Quartus 7.2,在上面进行过仿真，暂时还没有发现问题-Using Verilog HDL language written on the realization of the ADC, MDC control procedures, personal use Quartus 7.2, in the above simulation carried out have had no problems found
Platform: | Size: 1024 | Author: wangjiali | Hits:

[LabView] touch_key_adc.v

Description: TOUCH PAD KEY ADC CODE IN VERILOG
Platform: | Size: 4096 | Author: srikar | Hits:

[Other] ADS8329

Description: ADC芯片ADS8329数据采集的verilog代码，已经用在工程中，没问题。(ADC chip ADS8329 data acquisition Verilog code, has been used in the project, no problem.)
Platform: | Size: 1024 | Author: 麦子名兜 | Hits:

[VHDL-FPGA-Verilog] adc

Description: 使用verilog 硬件描述语言编写的ad采样模块，希望对大家有用。(Using Verilog hardware description language written in AD sampling module, I hope useful for everyone)
Platform: | Size: 6785024 | Author: ET@AF | Hits:

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