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[Other resource] ADPLL DL : 1: verilog ADPLL file with testbench.v
Update : 2008-10-13 Size : 25.04kb Publisher : 79979
[Other resource] adpll DL : 1: 全数字锁相环功能与74297相同提供参数配置
Update : 2008-10-13 Size : 2.01kb Publisher : lizhizhou
[VHDL-FPGA-Verilog] ADPLL DL : 2: verilog ADPLL file with testbench.v
Update : 2025-02-17 Size : 25kb Publisher :
[matlab] DPLL1lp DL : 0: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Update : 2025-02-17 Size : 8kb Publisher : rossi
[VHDL-FPGA-Verilog] adpll DL : 0: 全数字锁相环功能与74297相同提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
Update : 2025-02-17 Size : 2kb Publisher : lizhizhou
[VHDL-FPGA-Verilog] MinWinsockSpi DL : 0: verilog ADPLL file with testbench
Update : 2025-02-17 Size : 193kb Publisher : xgh
[VHDL-FPGA-Verilog] VCchuankou DL : 1: verilog ADPLL file with testbench
Update : 2025-02-17 Size : 202kb Publisher : xgh
[VHDL-FPGA-Verilog] a DL : 0: ADPLL of high level phase locked loop
Update : 2025-02-17 Size : 1.4mb Publisher : bc
[Other] b DL : 0: A high-speed variable phase accumulator for an ADPLL architecture
Update : 2025-02-17 Size : 281kb Publisher : bc
[VHDL-FPGA-Verilog] ADPLL DL : 1: 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。-All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
Update : 2025-02-17 Size : 2kb Publisher : 林飞
[Other] adpll DL : 0: All digital phase locked loop based clock multiplier design. No off chip components
Update : 2025-02-17 Size : 183kb Publisher : Abhishek
[SCM] APL99 DL : 0: An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery
Update : 2025-02-17 Size : 385kb Publisher : malijun
[Software Engineering] 10.1.1.125.4046 DL : 0: BUILDING AN RF SOURCE FOR LOW COST TESTERS USING AN ADPLL CONTROLLED BY TEXAS INSTRUMENTS DIGITAL SIGNAL
Update : 2025-02-17 Size : 86kb Publisher : Kidane
[Other] ADPLL DL : 0: 学习资料。一个关于信号处理软件ADPLL的使用说明，很有用。-Learning materials. A signal processing software ADPLL of the instructions, very useful.
Update : 2025-02-17 Size : 295kb Publisher : fu
[VHDL-FPGA-Verilog] a-adpll-based-on-fpga DL : 1: FPGA实现的VHDL语言的全数字锁相环-a adpll based on fpga
Update : 2025-02-17 Size : 4kb Publisher : MIMI
[File Format] ADPLL-patent DL : 1: 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
Update : 2025-02-17 Size : 402kb Publisher : 程硕
[ARM-PowerPC-ColdFire-MIPS] ADPLL DL : 0: verilog语言编写的fpga的全数字锁相环ADPLL程序-Verilog language FPGA all digital phase-locked loop ADPLL program
Update : 2025-02-17 Size : 264kb Publisher : 伊尔
[ELanguage] ADPLL DL : 0: code for a counter which is used in the design of a Digital Phase Locked Loop.
Update : 2025-02-17 Size : 18kb Publisher : Balakrishna C H