Description: Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be
implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design
time while FPGA based implementation offers lower cost, quicker and more customizable solution. This paper
represents implementing AES in FPGA with minimum latency and speedy throughput where Verilog HDL is used
to simulate the operations. Platform: |
Size: 218112 |
Author:arif |
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