Search - AHB - CodeBus

[MiddleWare] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98304 | Author: | Hits:

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[Software Engineering] CorePCIF_AHB_hb

Description: AHB to PCI Structure for FPGA/Asic Designer
Platform: | Size: 525312 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] SLAVERAM

Description: AHB slave 的一个简单的原型程序，通过参考该程序，可以写出相应的ahb slave 代码-AHB slave prototype of a simple procedure, by referring to the program, you can write the corresponding code ahb slave
Platform: | Size: 1024 | Author: goodboy2716 | Hits:

[Other] appnote65_quickmips_ahb_interface_design_example.r

Description: appnote65_quickmips_ahb_interface_design_example AHB接口设计-appnote65_quickmips_ahb_interface_design_exampleAHB Interface Design
Platform: | Size: 542720 | Author: Bill Guan | Hits:

[Other] ahb2ahb

Description: AMBA总线AHB TO AHB bridge-AMBA bus AHB TO AHB bridge
Platform: | Size: 2048 | Author: xiaoheng | Hits:

[VHDL-FPGA-Verilog] DW_8b10b_enc.v.tar

Description: amba ahb protocol with test benches
Platform: | Size: 3072 | Author: mahesh | Hits:

[Other] ahb_interface

Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
Platform: | Size: 540672 | Author: Bill Guan | Hits:

[Embeded-SCM Develop] ahb2wishbone_latest.tar

Description: opencore ahb to wishbone bus verilog code
Platform: | Size: 2662400 | Author: xiantongma | Hits:

[Documents] amba

Description: doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
Platform: | Size: 289792 | Author: ashish | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] ahb_master1

Description: this is a code of AMBA AHB master protocol in verilog
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] tb_ahb_master

Description: this is a AMBA AHB code for master.
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
Platform: | Size: 198656 | Author: guoxiaojin | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA-AHB-APB-BUS

Description: 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-depth understanding of
Platform: | Size: 50176 | Author: sp | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
Platform: | Size: 438272 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] AHB-BUS-AND-SLAVE-CODE-USING-VERILOG

Description: AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
Platform: | Size: 34816 | Author: xuqinjiang | Hits:

[VHDL-FPGA-Verilog] ahb

Description: verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
Platform: | Size: 36864 | Author: 落叶无情1992 | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] AHB-task-slave-master

Description: ahb master行为级模型，ahb slave模型(AHB master behavior level model, AHB slave model)
Platform: | Size: 2048 | Author: 鱼在在藻 | Hits:

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[MiddleWare] leon3-altera-ep2s60-sdr

[Other] ahb_system_generator.tar

[Software Engineering] CorePCIF_AHB_hb

[VHDL-FPGA-Verilog] SLAVERAM

[Other] appnote65_quickmips_ahb_interface_design_example.r

[Other] ahb2ahb

[VHDL-FPGA-Verilog] DW_8b10b_enc.v.tar

[Other] ahb_interface

[Embeded-SCM Develop] ahb2wishbone_latest.tar

[Documents] amba

[Video Capture] camera_up

[VHDL-FPGA-Verilog] ahb_master1

[VHDL-FPGA-Verilog] tb_ahb_master

[VHDL-FPGA-Verilog] AHB

[ARM-PowerPC-ColdFire-MIPS] AMBA-AHB-APB-BUS

[VHDL-FPGA-Verilog] AHB

[VHDL-FPGA-Verilog] AHB-BUS-AND-SLAVE-CODE-USING-VERILOG

[VHDL-FPGA-Verilog] ahb

[Other] AHB RAM

[VHDL-FPGA-Verilog] AHB-task-slave-master

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