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[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible \"muxed\" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new \"complex\" node.
Platform: | Size: 268999 | Author: 木石 | Hits:

[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[Other] ahb_interface

Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
Platform: | Size: 540672 | Author: Bill Guan | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
Platform: | Size: 438272 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] AHB-Arbiter-Module

Description: AMBA2.0版本AHB总线仲裁器设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB仲裁电路的接口、基本逻辑等方面进行介绍。-AMBA2.0、AHB Arbiter Module
Platform: | Size: 169984 | Author: 杨宗凯 | Hits:

[VHDL-FPGA-Verilog] AHBArbiter

Description: AMBA ahb总线协议的arbiter模块源代码，verilog编写，适合新手学习使用。-this is a code of AMBA AHB arbiter protocol in verilog
Platform: | Size: 2048 | Author: doody | Hits:

[VHDL-FPGA-Verilog] ahb

Description: 基于AMBA2.0的AHB 总线，包括arbiter，decoder，Muxs2m,Muxm2s-Based AMBA2.0 the AHB bus, including the arbiter, decoder, Muxs2m, Muxm2s
Platform: | Size: 10240 | Author: 李中星 | Hits:

[VHDL-FPGA-Verilog] ahb_system_generator_latest.tar

Description: AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.
Platform: | Size: 267264 | Author: Uthman | Hits:

[Other] Lecture10

Description: ahb master slave with arbiter decription
Platform: | Size: 434176 | Author: oxxy | Hits:

[Communication] verilog

Description: AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
Platform: | Size: 537600 | Author: zcvip1 | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
Platform: | Size: 17408 | Author: zhch26 | Hits:

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