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[Otherappnote65_quickmips_ahb_interface_design_example.r

Description: appnote65_quickmips_ahb_interface_design_example AHB接口设计-appnote65_quickmips_ahb_interface_design_exampleAHB Interface Design
Platform: | Size: 542720 | Author: Bill Guan | Hits:

[Video Capturecamera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备,另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号,然后下采样生成16bit RGB 5:6:5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转,以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范, AHB SLAVE接口,用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilogeth

Description: 一个ahb接口的千兆以太网MAC,包括apb的配置接口-Ahb a Gigabit Ethernet interface MAC, including the configuration interface apb
Platform: | Size: 31744 | Author: daisy | Hits:

[VHDL-FPGA-Verilogahb_ram

Description: AHB接口的ram控制器,可靠性非常强。除了两个周期内发生读到写或写到读的极限情况(一般处理器设计中不会有这种传输方式),其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem
Platform: | Size: 1024 | Author: Jasking Wu | Hits:

[VHDL-FPGA-VerilogAHB_slave-ram

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
Platform: | Size: 1024 | Author: 吴亮 | Hits:

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