Search - AHB master verilog

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[VHDL-FPGA-Verilog] ahb_master1

Description: this is a code of AMBA AHB master protocol in verilog
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] New

Description: amba ahb master decoder
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] masterdecoder

Description: AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 比较好的Verilog实现的AHB master。-Better AHB Verilog realization of the master.
Platform: | Size: 1024 | Author: 冯磊 | Hits:

[VHDL-FPGA-Verilog] AHB

Description: AMBA - AHB MASTER VERILOG CODE (UNCHECKED)
Platform: | Size: 15360 | Author: ilakiyareddy | Hits:

[VHDL-FPGA-Verilog] ahb_master

Description: AHB master system generator in verilog
Platform: | Size: 9216 | Author: Prashanth R | Hits:

[VHDL-FPGA-Verilog] ahb_bus

Description: ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
Platform: | Size: 28672 | Author: ross | Hits:

[Communication] verilog

Description: AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
Platform: | Size: 537600 | Author: zcvip1 | Hits:

[VHDL-FPGA-Verilog] ahb

Description: verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
Platform: | Size: 36864 | Author: 落叶无情1992 | Hits:

[VHDL-FPGA-Verilog] ahb_system_generator_latest.tar

Description: amba ahb master generator by using verilog
Platform: | Size: 268288 | Author: GADDAM | Hits:

[Other] AHB2-master

Description: verilog ahb master and slave
Platform: | Size: 31744 | Author: chandu1212 | Hits:

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[Other] ahb_system_generator.tar

[VHDL-FPGA-Verilog] ahb_master1

[VHDL-FPGA-Verilog] New

[VHDL-FPGA-Verilog] masterdecoder

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

[VHDL-FPGA-Verilog] AHB

[VHDL-FPGA-Verilog] AHB

[VHDL-FPGA-Verilog] ahb_master

[VHDL-FPGA-Verilog] ahb_bus

[Communication] verilog

[VHDL-FPGA-Verilog] ahb

[VHDL-FPGA-Verilog] ahb_system_generator_latest.tar

[Other] AHB2-master

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