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[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103163 | Author: 岳昆 | Hits:

[TCP/IP stack] altera_lwip

Description: 已移植到altera nios ii软核的基于microC/OS操作系统的lwip全套源代码- Transplanted to altera the nios ii soft nucleus based on microC/OS the operating system lwip complete set source code
Platform: | Size: 351232 | Author: 刘雅莎 | Hits:

[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103424 | Author: 岳昆 | Hits:

[VHDL-FPGA-Verilog] fpga_tcl

Description: Altera FPGA的特殊管脚的连接(中文).doc TCL_教程.pdf-Altera FPGA tcl
Platform: | Size: 629760 | Author: 朱柏 | Hits:

[VHDL-FPGA-Verilog] WallaceTreeImplementationInVHDL

Description: Wallace Tree Implementation in VHDL WT is one of the fastest way to implement multiplication of numbers in hardware design. (Optimized version) Tested in Altera 3.5u board by MonteCristo (H.U.T)
Platform: | Size: 6144 | Author: montecristo | Hits:

[VHDL-FPGA-Verilog] FPGA_TFT

Description: 使用FPGA驱动TFT液晶实现显示，开发环境为ALTERA公司的软件-Driven by the FPGA TFT LCD display, the software development environment for ALTERA
Platform: | Size: 110592 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] part1

Description: a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Platform: | Size: 140288 | Author: Henna Tan | Hits:

[Other Games] Ekran

Description: It is an Arkanoid game that is written by me in VHDL language. ı t is possible to play it via an altera FPGA and a monitor.
Platform: | Size: 10182656 | Author: Kaan Mutlu | Hits:

[Shot Game] craps

Description: this the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code-this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code
Platform: | Size: 23107584 | Author: darknight | Hits:

[Linux-Unix] altera-ci

Description: CI driver in conjunction with NetUp Dual DVB-T C RF CI card.
Platform: | Size: 6144 | Author: xqtuixr | Hits:

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