Search - AMBA VHDL

[Other resource] AMBAcode(vhdl)

Description: vhdl实现的amba代码
Platform: | Size: 201663 | Author: sk | Hits:

[VHDL-FPGA-Verilog] core_arm.tar

Description: 用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
Platform: | Size: 655360 | Author: 昭君 | Hits:

[MiddleWare] opencores_i2c_master

Description: i2c VHDL,能够实现I2C 用的是wishbone总线
Platform: | Size: 193536 | Author: wang | Hits:

[VHDL-FPGA-Verilog] adma.tar

Description: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
Platform: | Size: 12288 | Author: maliang | Hits:

[VHDL-FPGA-Verilog] AMBAcode(vhdl)

Description: vhdl实现的amba代码-realize the AMBA VHDL code
Platform: | Size: 201728 | Author: sk | Hits:

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] tb_ahb_master

Description: this is a AMBA AHB code for master.
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] New

Description: amba ahb master decoder
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] syncram_2p

Description: 这个一个基于amba总线的双端口ram的vhdl语言程序-The amba bus-based dual-port ram in vhdl language program
Platform: | Size: 2048 | Author: cws | Hits:

[VHDL-FPGA-Verilog] amba

Description: 这个一个基于amba总线的的vhdl语言程序描述，学习fpga总线开发的请看-The amba bus based on the procedures described in languages vhdl, fpga bus developed the study see
Platform: | Size: 3072 | Author: cws | Hits:

[VHDL-FPGA-Verilog] leon3

Description: 这个一个基于amba总线的leon3处理器的vhdl语言程序描述，学习fpga总线开发的请看-The amba bus-based processor vhdl language leon3 procedures described in the study developed fpga see bus
Platform: | Size: 2048 | Author: cws | Hits:

[VHDL-FPGA-Verilog] amba

Description: AMBA VHDL源代码.讲解的很详细，看看有什么可以借鉴的地方。-AMBA VHDL sourse
Platform: | Size: 35840 | Author: wusheer | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA_V2.0_CN

Description: ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
Platform: | Size: 1077248 | Author: 陶戈丹 | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: AMBA总线结构的VHDL代码 AMBA总线VHDL代码范例-AMBA BUS example
Platform: | Size: 6144 | Author: Yan Sun | Hits:

[Other] apb_slave

Description: AMBA 2.0 APB Example- SRAM -AMBA 2.0 APB Example- SRAM
Platform: | Size: 1024 | Author: Henry | Hits:

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[Other resource] AMBAcode(vhdl)

[VHDL-FPGA-Verilog] core_arm.tar

[MiddleWare] opencores_i2c_master

[VHDL-FPGA-Verilog] adma.tar

[VHDL-FPGA-Verilog] AMBAcode(vhdl)

[Video Capture] camera_up

[VHDL-FPGA-Verilog] tb_ahb_master

[VHDL-FPGA-Verilog] New

[VHDL-FPGA-Verilog] syncram_2p

[VHDL-FPGA-Verilog] amba

[VHDL-FPGA-Verilog] leon3

[VHDL-FPGA-Verilog] amba

[ARM-PowerPC-ColdFire-MIPS] AMBA_V2.0_CN

[VHDL-FPGA-Verilog] AMBA

[Other] apb_slave

[VHDL-FPGA-Verilog] AHB

[VHDL-FPGA-Verilog] AHBtoAPB

[VHDL-FPGA-Verilog] arm9verilog

[VHDL-FPGA-Verilog] a_vhdl_8253_timer_latest.tar

[VHDL-FPGA-Verilog] ahb_mas.tar

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