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[Other resource] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 71037 | Author: lile | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 70656 | Author: lile | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_alarmclock

Description:
Platform: | Size: 3252224 | Author: 廖耿耿 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE
Platform: | Size: 67584 | Author: hebin | Hits:

[VHDL-FPGA-Verilog] sARM01_07_12_2

Description: verilog hdl实现的ARM处理器-ARM processor implement by verilog HDL
Platform: | Size: 81920 | Author: lf | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Platform: | Size: 74752 | Author: shen jun | Hits:

[VHDL-FPGA-Verilog] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
Platform: | Size: 48128 | Author: xuyanwu | Hits:

[Other Embeded program] FIFO1

Description: 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据　(FIFO的宽度：也就是英文资料里常看到的THE  WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以存储8个8位的数据，深度为12，就可以存储12个8位的数据。)-Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.)
Platform: | Size: 33792 | Author: 江燕子 | Hits:

[VHDL-FPGA-Verilog] wARM

Description: 著名的wARM源代码，作者吴瑞祥，Verilog HDL源代码。(Famous wARM source code, author Wu Ruixiang Verilog, HDL source code.)
Platform: | Size: 6591488 | Author: fallrain116 | Hits:

[Other] eetop.cn_5个ARM_core

Description: 5 个ARM core HDL实现，设计的还不错(ARM core HDL implementation)
Platform: | Size: 1152000 | Author: 大刀牛角王 | Hits:

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