CodeBus
www.codebus.net
Search
Sign in
Sign up
Hot Search :
Source
embeded
web
remote control
p2p
game
More...
Location :
Home
Search - ATA verilog
Main Category
SourceCode
Documents
Books
WEB Code
Develop Tools
Other resource
Search - ATA verilog - List
[
Other resource
]
ata.tar
DL : 0
硬盘接口的硬件实现,VHDL和Verilog是吸纳的,带有文档!
Update
: 2008-10-13
Size
: 812.64kb
Publisher
:
刘志刚
[
Other resource
]
ata.tar
DL : 0
使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器,包括源代码、测试仿真文件和说明文档
Update
: 2008-10-13
Size
: 815.84kb
Publisher
:
qinlei
[
Other
]
ATA_source_code
DL : 0
ata控制器verilog源代码,入门的不错参考
Update
: 2008-10-13
Size
: 771.59kb
Publisher
:
范俊
[
Communication
]
基于USB-ATA接口的海量存储器的设计与实现
DL : 0
介绍了一种基于通用可编程接口的通用串行总线-高级技术配件解决方案,将普通硬盘转化为Usb Mass Storage.-introduces a general programmable interface based on the Universal Serial Bus-senior technical accessories solution that will drive into ordinary Usb Mass Storage.
Update
: 2025-02-17
Size
: 84kb
Publisher
:
蔡明
[
VHDL-FPGA-Verilog
]
ata.tar
DL : 0
硬盘接口的硬件实现,VHDL和Verilog是吸纳的,带有文档!-Hard disk interface hardware implementation, VHDL and Verilog is absorbed with documentation!
Update
: 2025-02-17
Size
: 813kb
Publisher
:
刘志刚
[
VHDL-FPGA-Verilog
]
ata.tar
DL : 0
使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器,包括源代码、测试仿真文件和说明文档-The use of two types of Verilog and VHDL hardware description language to achieve an ATA hard drive controller, including source code, testing, simulation files and documentation
Update
: 2025-02-17
Size
: 816kb
Publisher
:
qinlei
[
Other
]
ATA_source_code
DL : 0
ata控制器verilog源代码,入门的不错参考-ata controller Verilog source code, entry of a good reference
Update
: 2025-02-17
Size
: 771kb
Publisher
:
范俊
[
VHDL-FPGA-Verilog
]
ata.tar
DL : 0
PowerFull ATA Host Controller
Update
: 2025-02-17
Size
: 816kb
Publisher
:
esl
[
VC/MFC
]
report
DL : 0
Report about ATA standard that implement by verilog
Update
: 2025-02-17
Size
: 18kb
Publisher
:
pepekeke
[
source in ebook
]
Chapter1-5
DL : 0
第一章到第五章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update
: 2025-02-17
Size
: 1.51mb
Publisher
:
xiao
[
VHDL-FPGA-Verilog
]
Chapter6-9
DL : 0
第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update
: 2025-02-17
Size
: 5.99mb
Publisher
:
xiao
[
VHDL-FPGA-Verilog
]
Chapter10
DL : 0
第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Update
: 2025-02-17
Size
: 6.55mb
Publisher
:
xiao
[
VHDL-FPGA-Verilog
]
Chapter11-13
DL : 0
第十一章到第十三章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update
: 2025-02-17
Size
: 4.85mb
Publisher
:
xiao
[
Other
]
ata.tar
DL : 0
ATA Inteface Verilog Design
Update
: 2025-02-17
Size
: 816kb
Publisher
:
richman
CodeBus
is one of the largest source code repositories on the Internet!
Contact us :
1999-2046
CodeBus
All Rights Reserved.