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[Program doc] AXIprotocol

Description: AMBA AXI Protocol Specification
Platform: | Size: 749385 | Author: flipflop | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA

Description: SystemC写的AMBA 3.0 AXI总线事物级TLM模型 正在调试。有详细实验报告说明。-AMBA 3.0 AXI TLM SystemsC
Platform: | Size: 4893696 | Author: zhouli | Hits:

[USB develop] USB2.0

Description: USB2.0行为级描述，挂接在AMBA AXI总线上-USB2.0 RTL discription
Platform: | Size: 833536 | Author: liuwei | Hits:

[VHDL-FPGA-Verilog] BP062-BU-01000-r0p0-00rel0[1][1].tar

Description: AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
Platform: | Size: 313344 | Author: 李忠孝 | Hits:

[Windows Develop] System_Design_and_Implementation_of_AXI_Bus

Description: AMBA AXI资料，台湾硕士论文，网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
Platform: | Size: 1288192 | Author: kyle | Hits:

[Documents] AMBAaxi

Description: AXI spcialification document
Platform: | Size: 448512 | Author: superman | Hits:

[Software Engineering] AMBA-AXI

Description: ARM 内核总线的介绍。学习一下可以更加容易掌握ARM的知识-ARM core-bus introduction. And study how to more easily grasp the knowledge of ARM
Platform: | Size: 448512 | Author: chenhai | Hits:

[Embeded-SCM Develop] AMBA_axi_classic_protocol_document

Description: AMBA axi经典协议文档值得参考学习的资料AMBA axi classic protocol document-AMBA axi protocol documentation is also useful to study classical information AMBA axi classic protocol document
Platform: | Size: 399360 | Author: yuqa | Hits:

[VHDL-FPGA-Verilog] handshake

Description: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
Platform: | Size: 196608 | Author: nodeity | Hits:

[Linux-Unix] BP062

Description: This the AMBA® AXI Protocol v1.0 Source code-This is the AMBA® AXI Protocol v1.0 Source code
Platform: | Size: 300032 | Author: tamveso | Hits:

[source in ebook] AMBAaxi

Description: AMBA axi bus protocol: the documents for implementing AMBA axi
Platform: | Size: 401408 | Author: test | Hits:

[VHDL-FPGA-Verilog] AN151

Description: AMBA Application Note: AN151 - Using EB with example AXI Logic Tile. -AMBA Application Note: AN151- Using EB with example AXI Logic Tile. This example shows how to use the EB baseboard with an example AXI Logic Tile. The following board combinations are supported: Logic Tiles LT-XC2V6000 LT-XC2V8000 LT-XC4VLX160 LT-XC4VLX200 LT-XC5VLX330 running on top of baseboards EB+ CT1156T2F-S EB+ CT1176JZF-S EB+ CT11MPCore EB+ CT-R4F PB1176JZF-S PB11MPCore PB-A8 PBX-A9
Platform: | Size: 13879296 | Author: 余曉民 | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:

[VHDL-FPGA-Verilog] ppt

Description: 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
Platform: | Size: 637952 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] Micrium_Microblaze_uCOS-II-AXI

Description: 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
Platform: | Size: 228352 | Author: xuzhengshan | Hits:

[] AMBA AXI and ACE Protocol Specification.pdf

Description: AMBA AXI and ACE Protocol Specification
Platform: | Size: 1219584 | Author: thekkk | Hits:

[] AMBA 3 AXI Protocol Specification.pdf

Description: AMBA 3 AXI Specification
Platform: | Size: 409600 | Author: thekkk | Hits:

[VHDL-FPGA-Verilog] AXI-HP-ZYNQ

Description: 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)
Platform: | Size: 32524288 | Author: 刘小娃 | Hits:

[VHDL-FPGA-Verilog] AXI-full

Description: axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
Platform: | Size: 8192 | Author: 橙子很好吃 | Hits:

[VHDL-FPGA-Verilog] verilog-axi-master

Description: Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi
Platform: | Size: 313344 | Author: viyefo5674 | Hits:
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